公开(公告)号：US20230187515A1

公开(公告)日：2023-06-15

申请号：US17549550

申请日：2021-12-13

申请人： Sukru YEMENICIOGLU ,  Tahir GHANI ,  Xinning WANG ,  Leonard P. GULER ,  Charles H. WALLACE ,  Mohit K. HARAN

发明人： Sukru YEMENICIOGLU ,  Tahir GHANI ,  Xinning WANG ,  Leonard P. GULER ,  Charles H. WALLACE ,  Mohit K. HARAN

IPC分类号： H01L29/423 ,  H01L27/092 ,  H01L29/786 ,  H01L29/06

CPC分类号： H01L29/42392 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/78696

摘要： Described herein are integrated circuit structures having versatile channel placement, and methods of fabricating integrated circuit structures having versatile channel placement. In an example, an integrated circuit structure includes a first vertical stack of horizontal nanowires having a first width. A second vertical stack of horizontal nanowires is immediately neighboring and parallel with the first vertical stack of horizontal nanowires and has a second width greater than the first width. A third vertical stack of horizontal nanowires is immediately neighboring and parallel with the second vertical stack of horizontal nanowires and has the first width.

公开(公告)号：US20230207466A1

公开(公告)日：2023-06-29

申请号：US17561717

申请日：2021-12-24

申请人： Leonard P. GULER ,  Jeffrey S. LEIB ,  Chanaka D. MUNASINGHE ,  Charles H. WALLACE ,  Tahir GHANI ,  Mohit K. HARAN

发明人： Leonard P. GULER ,  Jeffrey S. LEIB ,  Chanaka D. MUNASINGHE ,  Charles H. WALLACE ,  Tahir GHANI ,  Mohit K. HARAN

IPC分类号： H01L23/528 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

CPC分类号： H01L23/5286 ,  H01L29/0665 ,  H01L29/785 ,  H01L29/42392

摘要： Embodiments include semiconductor devices. In an embodiment, a semiconductor device comprises a first non-planar transistor over a substrate and a second non-planar transistor over the substrate and parallel to the first non-planar transistor. In an embodiment, a gate structure is over the first non-planar transistor and the second non-planar transistor. In an embodiment, a power rail is between the first non-planar transistor and the second non-planar transistor. In an embodiment, a top surface of the power rail is below a top surface of a gate structure.

公开(公告)号：US20230197609A1

公开(公告)日：2023-06-22

申请号：US17554456

申请日：2021-12-17

申请人： Sukru YEMENICIOGLU ,  Charles H. WALLACE ,  Mohit K. HARAN ,  Seung-June CHOI

发明人： Sukru YEMENICIOGLU ,  Charles H. WALLACE ,  Mohit K. HARAN ,  Seung-June CHOI

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC分类号： H01L23/5283 ,  H01L23/5226 ,  H01L21/76816 ,  H01L21/76885

摘要： Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes an interlayer dielectric layer. A plurality of parallel conductive lines is in the interlayer dielectric layer. The plurality of parallel conductive lines includes a first conductive line and a second conductive line. The first conductive line includes breaks therein with first and second dielectric plugs separating portions of the first conductive line, one of the portions between the first dielectric plug and the second dielectric plug and having a first dimension. The second conductive line includes first and second conductive line portions separated by an intervening conductive via structure, the conductive via structure separated from the first and second conductive line portions, and the conductive via structure having a second dimension parallel with the first dimension, the second dimension less than the first dimension.