公开(公告)号：US20230187515A1

公开(公告)日：2023-06-15

申请号：US17549550

申请日：2021-12-13

申请人： Sukru YEMENICIOGLU ,  Tahir GHANI ,  Xinning WANG ,  Leonard P. GULER ,  Charles H. WALLACE ,  Mohit K. HARAN

发明人： Sukru YEMENICIOGLU ,  Tahir GHANI ,  Xinning WANG ,  Leonard P. GULER ,  Charles H. WALLACE ,  Mohit K. HARAN

IPC分类号： H01L29/423 ,  H01L27/092 ,  H01L29/786 ,  H01L29/06

CPC分类号： H01L29/42392 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/78696

摘要： Described herein are integrated circuit structures having versatile channel placement, and methods of fabricating integrated circuit structures having versatile channel placement. In an example, an integrated circuit structure includes a first vertical stack of horizontal nanowires having a first width. A second vertical stack of horizontal nanowires is immediately neighboring and parallel with the first vertical stack of horizontal nanowires and has a second width greater than the first width. A third vertical stack of horizontal nanowires is immediately neighboring and parallel with the second vertical stack of horizontal nanowires and has the first width.

公开(公告)号：US20230187444A1

公开(公告)日：2023-06-15

申请号：US17549530

申请日：2021-12-13

申请人： Sukru YEMENICIOGLU ,  Xinning WANG ,  Allen B. GARDINER ,  Tahir GHANI ,  Mohit K. HARAN ,  Leonard P. GULER

发明人： Sukru YEMENICIOGLU ,  Xinning WANG ,  Allen B. GARDINER ,  Tahir GHANI ,  Mohit K. HARAN ,  Leonard P. GULER

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

CPC分类号： H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823871 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742

摘要： Integrated circuit structures having gate cut offset, and methods of fabricating integrated circuit structures having gate cut offset, are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowires. A second vertical stack of horizontal nanowires is spaced apart from and parallel with the first vertical stack of horizontal nanowires. A gate structure includes a first gate structure portion over the first vertical stack of horizontal nanowires, a second gate structure over the second vertical stack of horizontal nanowires, and a gate cut between the first gate structure portion and the second gate structure portion, the gate cut laterally closer to the second vertical stack of horizontal nanowires than to the first vertical stack of horizontal nanowires.

公开(公告)号：US20230207466A1

公开(公告)日：2023-06-29

申请号：US17561717

申请日：2021-12-24

申请人： Leonard P. GULER ,  Jeffrey S. LEIB ,  Chanaka D. MUNASINGHE ,  Charles H. WALLACE ,  Tahir GHANI ,  Mohit K. HARAN

发明人： Leonard P. GULER ,  Jeffrey S. LEIB ,  Chanaka D. MUNASINGHE ,  Charles H. WALLACE ,  Tahir GHANI ,  Mohit K. HARAN

IPC分类号： H01L23/528 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

CPC分类号： H01L23/5286 ,  H01L29/0665 ,  H01L29/785 ,  H01L29/42392

摘要： Embodiments include semiconductor devices. In an embodiment, a semiconductor device comprises a first non-planar transistor over a substrate and a second non-planar transistor over the substrate and parallel to the first non-planar transistor. In an embodiment, a gate structure is over the first non-planar transistor and the second non-planar transistor. In an embodiment, a power rail is between the first non-planar transistor and the second non-planar transistor. In an embodiment, a top surface of the power rail is below a top surface of a gate structure.

公开(公告)号：US20230207704A1

公开(公告)日：2023-06-29

申请号：US17561589

申请日：2021-12-23

申请人： Dan S. LAVRIC ,  YenTing CHIU ,  Mohit K. HARAN ,  Allen B. GARDINER ,  Leonard P. GULER ,  Andy Chih-Hung WEI ,  Tahir GHANI

发明人： Dan S. LAVRIC ,  YenTing CHIU ,  Mohit K. HARAN ,  Allen B. GARDINER ,  Leonard P. GULER ,  Andy Chih-Hung WEI ,  Tahir GHANI

IPC分类号： H01L29/808 ,  H01L29/80 ,  H01L29/78

CPC分类号： H01L29/808 ,  H01L29/802 ,  H01L29/783

摘要： Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to integrated circuits with self-aligned tub architectures. Other embodiments may be described or claimed.

公开(公告)号：US20230197855A1

公开(公告)日：2023-06-22

申请号：US17557995

申请日：2021-12-21

申请人： Mohammad HASAN ,  Nitesh KUMAR ,  Rushabh SHAH ,  Anand S. MURTHY ,  Pratik PATEL ,  Leonard P. GULER ,  Tahir GHANI

发明人： Mohammad HASAN ,  Nitesh KUMAR ,  Rushabh SHAH ,  Anand S. MURTHY ,  Pratik PATEL ,  Leonard P. GULER ,  Tahir GHANI

IPC分类号： H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC分类号： H01L29/78618 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

摘要： Gate-all-around integrated circuit structures having source or drain structures with regrown central portions, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with regrown central portions, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. A gate stack is over the vertical arrangements of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. One or both of the first or second epitaxial source or drain structures has a central portion within an outer portion, and an interface between the central portion and the outer portion.

公开(公告)号：US20230197838A1

公开(公告)日：2023-06-22

申请号：US17558046

申请日：2021-12-21

申请人： Mohammad HASAN ,  Leonard P. GULER ,  Anand S. Murthy ,  Pratik PATEL ,  Tahir GHANI

发明人： Mohammad HASAN ,  Leonard P. GULER ,  Anand S. Murthy ,  Pratik PATEL ,  Tahir GHANI

IPC分类号： H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L29/775 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/02532 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66439

摘要： Gate-all-around integrated circuit structures having source or drain-last structures, and methods of fabricating gate-all-around integrated circuit structures having source or drain-last structures, are described. For example, a method of fabricating an integrated circuit structure includes forming a vertical arrangement of nanowires. A permanent gate stack is then formed over the vertical arrangements of nanowires. The permanent gate stack includes a high-k gate dielectric layer and a metal gate electrode. Subsequent to forming the permanent gate stack, a first epitaxial source or drain structure is formed at a first end of the vertical arrangement of nanowires, and a second epitaxial source or drain structure is formed at a second end of the vertical arrangement of nanowires.

公开(公告)号：US20200098878A1

公开(公告)日：2020-03-26

申请号：US16139252

申请日：2018-09-24

申请人： Leonard P. GULER ,  Biswajeet GUHA ,  Tahir GHANI ,  Swaminathan SIVAKUMAR

发明人： Leonard P. GULER ,  Biswajeet GUHA ,  Tahir GHANI ,  Swaminathan SIVAKUMAR

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088

摘要： Self-aligned gate endcap architectures with gate-all-around devices having epitaxial source or drain structures are described. For example, a structure includes first and second vertical arrangements of nanowires, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stacks are over the first and second vertical arrangements of nanowires, respectively. A gate endcap isolation structure is between the first and second gate stacks, respectively. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires and have an uppermost surface below an uppermost surface of the gate endcap isolation structure. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires and have an uppermost surface below the uppermost surface of the gate endcap isolation structure.

公开(公告)号：US20190393352A1

公开(公告)日：2019-12-26

申请号：US16017966

申请日：2018-06-25

申请人： Biswajeet GUHA ,  William HSU ,  Leonard P. GULER ,  Dax M. CRUM ,  Tahir GHANI

发明人： Biswajeet GUHA ,  William HSU ,  Leonard P. GULER ,  Dax M. CRUM ,  Tahir GHANI

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L21/02 ,  H01L21/8234 ,  H01L23/522

摘要： Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.