公开(公告)号：US20150293835A1

公开(公告)日：2015-10-15

申请号：US14680337

申请日：2015-04-07

申请人： Sung-Boem PARK ,  Jin-Sung PARK ,  Ara CHO

发明人： Sung-Boem PARK ,  Jin-Sung PARK ,  Ara CHO

IPC分类号： G06F11/36 ,  G06F9/44

CPC分类号： G06F9/3865 ,  G06F9/30145 ,  G06F11/3688

摘要： A verification method of a system on chip includes receiving a test generator and an exception handler; generating, by the test generator, a test program including an exception-causing instruction based on a test template; executing a first instruction at a first operating state as the test program is executed; stopping the execution of the test program and performing a fixed instruction sequence included in the exception handler when the exception-causing instruction is executed during the execution of the test program; and resuming the test program from a second instruction at a second operating state set after the fixed instruction sequence is performed, the second instruction corresponding to an address adjacent to an address of the exception-causing instruction.

摘要翻译： 芯片上的系统的验证方法包括接收测试发生器和异常处理程序; 由测试发生器产生包括基于测试模板的异常指令的测试程序; 在执行测试程序时在第一操作状态下执行第一指令; 当在执行测试程序期间执行异常指令时，停止执行测试程序并执行包括在异常处理程序中的固定指令序列; 以及在执行所述固定指令序列之后设置的第二操作状态下从第二指令恢复所述测试程序，所述第二指令对应于与所述异常指令的地址相邻的地址。

公开(公告)号：US20090252623A1

公开(公告)日：2009-10-08

申请号：US12416277

申请日：2009-04-01

申请人： Jong-Yoon CHOI ,  Kyeong-Bae PARK ,  Ki-Chul CHOI ,  Eon-Pyo HONG ,  Jin-Sung PARK

发明人： Jong-Yoon CHOI ,  Kyeong-Bae PARK ,  Ki-Chul CHOI ,  Eon-Pyo HONG ,  Jin-Sung PARK

IPC分类号： F04B35/04 ,  H02K33/16

CPC分类号： H02K33/02 ,  F04B35/045 ,  H02K1/145

摘要： A reciprocating motor and a reciprocating compressor having the same are provided. One side of each of outer and inner cores forming a stator are connected to each other, to prevent a magnetic flux generated by the coil and a magnet from leaking out of the stator. Hence, it is possible to fabricate components of the reciprocating compressor employing such a reciprocating motor by using a relatively low-cost magnetic substance, resulting in a decrease in fabricating costs of the compressor. Also, a length of the magnet may be reduced, which results in a reduction of the cost for the magnet, thereby decreasing fabricating costs of the reciprocating motor and the reciprocating compressor employing the reciprocating motor.

摘要翻译： 提供了一种往复式电动机和具有该往复式电动机的往复式压缩机。 形成定子的每个外芯和内芯的一侧彼此连接，以防止由线圈产生的磁通和磁体从定子泄漏。 因此，可以通过使用相对低成本的磁性物质来制造使用这种往复式电动机的往复式压缩机的部件，导致压缩机的制造成本降低。 此外，可以减小磁体的长度，这导致磁体成本的降低，从而降低往复式电动机和使用往复式电动机的往复式压缩机的制造成本。

公开(公告)号：US20090040822A1

公开(公告)日：2009-02-12

申请号：US12255825

申请日：2008-10-22

申请人： Seung-Jae LEE ,  Jin-Sung PARK

发明人： Seung-Jae LEE ,  Jin-Sung PARK

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2216/14

摘要： A flash memory device is provided, and the flash memory device comprises memory cells, a sense node connected to a selected bit line, a load circuit connected to the sense node, and first and second sense and register circuits, each connected to the sense node. The first sense and register circuit is configured to store a first data value in accordance with the voltage level of the sense node during an initial read interval of a multi-bit program operation. The load circuit is configured to selectively pre-charge the sense node in accordance with the data value stored in the first sense and register circuit during a verify read interval of the multi-bit program operation. A multi-bit programming method for the flash memory device is also provided.

摘要翻译： 提供闪速存储器件，并且闪速存储器件包括存储器单元，连接到所选位线的感测节点，连接到感测节点的负载电路以及连接到感测节点的第一和第二感测和寄存器电路 。 第一感测和寄存器电路被配置为在多位程序操作的初始读取间隔期间根据感测节点的电压电平来存储第一数据值。 负载电路被配置为在多位程序操作的验证读取间隔期间根据存储在第一感测和寄存器电路中的数据值选择性地预充电感测节点。 还提供了一种用于闪速存储器件的多位编程方法。

公开(公告)号：US20090225600A1

公开(公告)日：2009-09-10

申请号：US12100490

申请日：2008-04-10

申请人： Jin-Sung PARK

发明人： Jin-Sung PARK

IPC分类号： G11C16/04 ,  G11C7/00 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

摘要： A flash memory device that includes a voltage generator circuit configured to generate a program voltage, a pass voltage, and a high voltage; a plurality of planes configured to perform a program operation in response to the program, pass, and high voltages and to verify the program operation, respectively; and control logic configured to control the planes in response to verification results from the planes, wherein the control logic controls the planes so as to interrupt the program and pass voltages or the high voltage from being applied to program-passed planes.

摘要翻译： 一种闪速存储装置，包括：电压发生器电路，被配置为产生编程电压，通过电压和高电压; 配置为响应于程序执行程序操作的多个平面，通过和高电压并且分别验证程序操作; 以及控制逻辑，其被配置为响应于来自所述平面的验证结果来控制所述平面，其中所述控制逻辑控制所述平面，以便中断所述程序并将电压或所述高电压施加到程序传递平面。