公开(公告)号：US07553748B2

公开(公告)日：2009-06-30

申请号：US11463812

申请日：2006-08-10

申请人： Sung-Ho Jang ,  Sang-Ho Song ,  Sung-Sam Lee ,  Min-Sung Kang ,  Won-Tae Park ,  Min-Young Shim

发明人： Sung-Ho Jang ,  Sang-Ho Song ,  Sung-Sam Lee ,  Min-Sung Kang ,  Won-Tae Park ,  Min-Young Shim

IPC分类号： H01L21/20

CPC分类号： H01L21/76897 ,  H01L27/10876 ,  H01L29/7834

摘要： According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to form a semiconductor device. A spacer is formed on a surface of the gate structure. An insulating interlayer pattern is formed on the substrate including the gate structure, and an opening is formed through the insulating interlayer pattern corresponding to an impurity region of the substrate. A conductive pattern is formed in the opening and a top surface thereof is higher than a top surface of the insulating interlayer pattern. Thus, an upper portion of the conductive pattern is protruded from the insulating interlayer pattern. A capping pattern is formed on the insulating interlayer pattern, and a sidewall of the protruded portion of the conductive pattern is covered with the capping pattern. Accordingly, the capping pattern compensates for a thickness reduction of the gate mask.

摘要翻译： 根据一个实施例，在衬底的沟道区上形成包括栅极绝缘图案，栅极图案和栅极掩模的栅极结构，以形成半导体器件。 在栅极结构的表面上形成间隔物。 在包括栅极结构的基板上形成绝缘层间图案，并且通过与基板的杂质区域对应的绝缘层间图案形成开口。 在开口中形成导电图案，其顶表面高于绝缘层间图案的顶表面。 因此，导电图案的上部从绝缘层间图案突出。 在绝缘层间图案上形成封盖图案，并且用封盖图案覆盖导电图案的突出部分的侧壁。 因此，封盖图案补偿了栅极掩模的厚度减小。