公开(公告)号：US07553748B2

公开(公告)日：2009-06-30

申请号：US11463812

申请日：2006-08-10

申请人： Sung-Ho Jang ,  Sang-Ho Song ,  Sung-Sam Lee ,  Min-Sung Kang ,  Won-Tae Park ,  Min-Young Shim

发明人： Sung-Ho Jang ,  Sang-Ho Song ,  Sung-Sam Lee ,  Min-Sung Kang ,  Won-Tae Park ,  Min-Young Shim

IPC分类号： H01L21/20

CPC分类号： H01L21/76897 ,  H01L27/10876 ,  H01L29/7834

摘要： According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to form a semiconductor device. A spacer is formed on a surface of the gate structure. An insulating interlayer pattern is formed on the substrate including the gate structure, and an opening is formed through the insulating interlayer pattern corresponding to an impurity region of the substrate. A conductive pattern is formed in the opening and a top surface thereof is higher than a top surface of the insulating interlayer pattern. Thus, an upper portion of the conductive pattern is protruded from the insulating interlayer pattern. A capping pattern is formed on the insulating interlayer pattern, and a sidewall of the protruded portion of the conductive pattern is covered with the capping pattern. Accordingly, the capping pattern compensates for a thickness reduction of the gate mask.

摘要翻译： 根据一个实施例，在衬底的沟道区上形成包括栅极绝缘图案，栅极图案和栅极掩模的栅极结构，以形成半导体器件。 在栅极结构的表面上形成间隔物。 在包括栅极结构的基板上形成绝缘层间图案，并且通过与基板的杂质区域对应的绝缘层间图案形成开口。 在开口中形成导电图案，其顶表面高于绝缘层间图案的顶表面。 因此，导电图案的上部从绝缘层间图案突出。 在绝缘层间图案上形成封盖图案，并且用封盖图案覆盖导电图案的突出部分的侧壁。 因此，封盖图案补偿了栅极掩模的厚度减小。

公开(公告)号：US07465988B2

公开(公告)日：2008-12-16

申请号：US11871876

申请日：2007-10-12

申请人： Sung-Sam Lee ,  Yong-Tae Kim ,  Mi-Youn Kim ,  Gyo-Young Jin ,  Dae-Won Ha ,  Yun-Gi Kim

发明人： Sung-Sam Lee ,  Yong-Tae Kim ,  Mi-Youn Kim ,  Gyo-Young Jin ,  Dae-Won Ha ,  Yun-Gi Kim

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/823437 ,  H01L21/823481

摘要： A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction. Consequently, leaning of the dummy region and void migration are prevented. A method of fabricating the semiconductor device is also provided.

摘要翻译： 提供能够抑制空穴迁移的半导体器件。 半导体器件包括在基本上垂直于字线延伸的第二方向的第一方向上延伸的虚拟区域。 此外，隔离层图案可以不在第二方向上切割伪区域。 因此，防止虚拟区域的倾斜和空隙迁移。 还提供了制造半导体器件的方法。

公开(公告)号：US20080054353A1

公开(公告)日：2008-03-06

申请号：US11849900

申请日：2007-09-04

申请人： Ho-Jin OH ,  Sung-Sam LEE ,  Bong-Cheol KIM

发明人： Ho-Jin OH ,  Sung-Sam LEE ,  Bong-Cheol KIM

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/06

CPC分类号： H01L21/823437 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/7834

摘要： A semiconductor device includes a semiconductor substrate and recess trenches formed on the semiconductor substrate. The recess trenches are arranged to extend along a first direction. Terminal regions of adjacent ones of the recess trenches are offset relative to each other along a second direction substantially perpendicular to the first direction.

摘要翻译： 半导体器件包括半导体衬底和形成在半导体衬底上的凹槽。 凹槽被布置成沿着第一方向延伸。 相邻的凹槽的端子区域沿着基本上垂直于第一方向的第二方向相对于彼此偏移。

公开(公告)号：US20070042583A1

公开(公告)日：2007-02-22

申请号：US11463812

申请日：2006-08-10

申请人： Sung-Ho JANG ,  Sang-Ho SONG ,  Sung-Sam LEE ,  Min-Sung KANG ,  Won-Tae PARK ,  Min-Young SHIM

发明人： Sung-Ho JANG ,  Sang-Ho SONG ,  Sung-Sam LEE ,  Min-Sung KANG ,  Won-Tae PARK ,  Min-Young SHIM

IPC分类号： H01L21/3205

CPC分类号： H01L21/76897 ,  H01L27/10876 ,  H01L29/7834

摘要： According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to form a semiconductor device. A spacer is formed on a surface of the gate structure. An insulating interlayer pattern is formed on the substrate including the gate structure, and an opening is formed through the insulating interlayer pattern corresponding to an impurity region of the substrate. A conductive pattern is formed in the opening and a top surface thereof is higher than a top surface of the insulating interlayer pattern. Thus, an upper portion of the conductive pattern is protruded from the insulating interlayer pattern. A capping pattern is formed on the insulating interlayer pattern, and a sidewall of the protruded portion of the conductive pattern is covered with the capping pattern. Accordingly, the capping pattern compensates for a thickness reduction of the gate mask.

摘要翻译： 根据一个实施例，在衬底的沟道区上形成包括栅极绝缘图案，栅极图案和栅极掩模的栅极结构，以形成半导体器件。 在栅极结构的表面上形成间隔物。 在包括栅极结构的基板上形成绝缘层间图案，并且通过与基板的杂质区域对应的绝缘层间图案形成开口。 在开口中形成导电图案，其顶表面高于绝缘层间图案的顶表面。 因此，导电图案的上部从绝缘层间图案突出。 在绝缘层间图案上形成封盖图案，并且用封盖图案覆盖导电图案的突出部分的侧壁。 因此，封盖图案补偿了栅极掩模的厚度减小。

公开(公告)号：US08426274B2

公开(公告)日：2013-04-23

申请号：US12861247

申请日：2010-08-23

申请人： Jun-Ho Yoon ,  Kyoung-Sub Shin ,  Sung-Sam Lee ,  Kung-Hyon Nam ,  Hong Cho ,  Joon-Seok Moon

发明人： Jun-Ho Yoon ,  Kyoung-Sub Shin ,  Sung-Sam Lee ,  Kung-Hyon Nam ,  Hong Cho ,  Joon-Seok Moon

IPC分类号： H01L21/336 ,  H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/02238 ,  H01L21/3065 ,  H01L29/66621

摘要： Example embodiments relate to a method of forming a recess and a method of manufacturing a semiconductor device having the same. The method includes forming a field region defining an active region in a substrate. The active region extends in a first direction in the substrate. The method further includes forming a preliminary recess extending in a second direction different from the first direction and crossing the active region in the substrate, plasma-oxidizing the substrate to form a sacrificial oxide layer along a surface of the substrate having the preliminary recess, and removing portions of the sacrificial oxide layer and the active region by plasma etching to form a recess having a width larger than a width of the preliminary recess, where an etch rate of the active region is one to two times greater than an etch rate of the sacrificial oxide layer.

摘要翻译： 示例性实施例涉及形成凹部的方法和制造具有该凹部的半导体器件的方法。 该方法包括形成在衬底中限定有源区的场区域。 有源区在衬底中沿第一方向延伸。 所述方法还包括形成在与所述第一方向不同的第二方向上延伸并且与所述衬底中的有源区交叉的预备凹槽，等离子体氧化所述衬底以沿着具有所述初步凹槽的所述衬底的表面形成牺牲氧化物层，以及 通过等离子体蚀刻去除牺牲氧化物层和有源区的部分以形成具有大于初步凹槽的宽度的宽度的凹部，其中有源区的蚀刻速率是其中的蚀刻速率的一到两倍 牺牲氧化层。

公开(公告)号：US08035136B2

公开(公告)日：2011-10-11

申请号：US12508305

申请日：2009-07-23

申请人： Sung-Sam Lee ,  Joon-Seok Moon ,  Young-Ju Choi

发明人： Sung-Sam Lee ,  Joon-Seok Moon ,  Young-Ju Choi

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L28/91 ,  H01L21/823437 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10876 ,  H01L28/65

摘要： In a semiconductor device and a method of manufacturing the same, a substrate is defined into active and non-active regions by a device isolation layer and a recessed portion is formed on the active region. A gate electrode includes a gate insulation layer on an inner sidewall and a bottom of the recessed portion, a lower electrode on the gate insulation layer and an inner spacer on the lower electrode in the recessed portion, and an upper electrode that is positioned on the inner spacer and connected to the lower electrode. Source and drain impurity regions are formed at surface portions of the active region of the substrate adjacent to the upper electrode. Accordingly, the source and drain impurity regions are electrically insulated by the inner spacer in the recessed portion of the substrate like a bridge, to thereby sufficiently prevent gate-induced drain leakage (GIDL) at the gate electrode.

摘要翻译： 在半导体器件及其制造方法中，通过器件隔离层将衬底限定为有源区域和非有源区域，并且在有源区域上形成凹部。 栅极电极包括在内侧壁和凹部的底部上的栅极绝缘层，栅极绝缘层上的下部电极和凹部中的下部电极上的内部间隔物，以及位于 内部间隔件并连接到下部电极。 源极和漏极杂质区形成在与上电极相邻的衬底的有源区的表面部分处。 因此，源极和漏极杂质区域如桥接在衬底的凹陷部分中的内部间隔物电绝缘，从而充分防止栅电极处的栅极引起的漏极泄漏（GIDL）。

公开(公告)号：US07297596B2

公开(公告)日：2007-11-20

申请号：US11552359

申请日：2006-10-24

申请人： Sung-Sam Lee ,  Yong-Tae Kim ,  Mi-Youn Kim ,  Gyo-Young Jin ,  Dae-Won Ha ,  Yun-Gi Kim

发明人： Sung-Sam Lee ,  Yong-Tae Kim ,  Mi-Youn Kim ,  Gyo-Young Jin ,  Dae-Won Ha ,  Yun-Gi Kim

IPC分类号： H01L21/336

CPC分类号： H01L21/823437 ,  H01L21/823481

摘要： A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction. Consequently, leaning of the dummy region and void migration are prevented. A method of fabricating the semiconductor device is also provided.

摘要翻译： 提供能够抑制空穴迁移的半导体器件。 半导体器件包括在基本上垂直于字线延伸的第二方向的第一方向上延伸的虚拟区域。 此外，隔离层图案可以不在第二方向上切割伪区域。 因此，防止虚拟区域的倾斜和空隙迁移。 还提供了制造半导体器件的方法。

公开(公告)号：US20060263991A1

公开(公告)日：2006-11-23

申请号：US11383141

申请日：2006-05-12

申请人： Sung-Sam LEE ,  Gyo-Young JIN ,  Yun-Gi KIM

发明人： Sung-Sam LEE ,  Gyo-Young JIN ,  Yun-Gi KIM

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L21/76232

摘要： In one embodiment, a semiconductor device has an active region defined by an isolation layer formed inside an STI trench that includes an upper trench and a lower trench having a substantially curved cross-sectional profile under the upper trench so that the lower trench is in communication with the upper trench. Since the upper trench has a sidewall tapered with a positive slope, a good gap filling property can be obtained when filling the upper trench with an insulating layer. By forming a void in the lower trench, a dielectric constant at the bottom of the isolation layer is lower than a dielectric constant at an oxide layer, thereby improving the isolation property. The isolation layer includes a first insulating layer formed inside only the upper trench and covering an inner wall of the upper trench in the form of a spacer.

摘要翻译： 在一个实施例中，半导体器件具有由形成在STI沟槽内部的隔离层限定的有源区，该隔离层包括上沟槽和下沟槽，所述上沟槽和下沟槽在所述上沟槽下方具有基本弯曲的横截面轮廓，使得所述下沟槽处于连通状态 与上沟槽。 由于上沟槽具有以正斜率渐缩的侧壁，因此当用绝缘层填充上沟槽时，可以获得良好的间隙填充性能。 通过在下沟槽中形成空隙，隔离层底部的介电常数低于氧化物层的介电常数，从而提高隔离性能。 隔离层包括仅在上沟槽内形成的第一绝缘层，并且以间隔物的形式覆盖上沟槽的内壁。

公开(公告)号：US07902597B2

公开(公告)日：2011-03-08

申请号：US12025877

申请日：2008-02-05

申请人： Sung-Sam Lee ,  Min-Hee Cho

发明人： Sung-Sam Lee ,  Min-Hee Cho

IPC分类号： H01L21/336

CPC分类号： H01L29/66621 ,  H01L21/76232 ,  H01L21/823481 ,  H01L29/78

摘要： A transistor and method of fabricating the transistor are disclosed. The transistor is disposed in an active region of a substrate defined by an isolation region and includes a gate electrode and associated source/drain regions. The isolation region includes an upper isolation region and an lower isolation region, wherein the upper isolation region is formed with sidewalls having, at least in part, a positive profile.

摘要翻译： 公开了晶体管和晶体管的制造方法。 晶体管设置在由隔离区域限定的衬底的有源区域中，并且包括栅极电极和相关的源极/漏极区域。 隔离区域包括上部隔离区域和下部隔离区域，其中上部隔离区域形成有具有至少部分至少部分为正形状的侧壁。

公开(公告)号：US20080157194A1

公开(公告)日：2008-07-03

申请号：US12025877

申请日：2008-02-05

申请人： Sung-Sam LEE ,  Min-Hee CHO

发明人： Sung-Sam LEE ,  Min-Hee CHO

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66621 ,  H01L21/76232 ,  H01L21/823481 ,  H01L29/78

摘要： A transistor and method of fabricating the transistor are disclosed. The transistor is disposed in an active region of a substrate defined by an isolation region and includes a gate electrode and associated source/drain regions. The isolation region includes an upper isolation region and an lower isolation region, wherein the upper isolation region is formed with sidewalls having, at least in part, a positive profile.

摘要翻译： 公开了晶体管和晶体管的制造方法。 晶体管设置在由隔离区域限定的衬底的有源区域中，并且包括栅极电极和相关的源极/漏极区域。 隔离区域包括上部隔离区域和下部隔离区域，其中上部隔离区域形成有具有至少部分至少部分为正形状的侧壁。