公开(公告)号：US06787906B1

公开(公告)日：2004-09-07

申请号：US09699589

申请日：2000-10-30

申请人： Won-Suk Yang ,  Sang-Ho Song ,  Hong-Sik Jeong ,  Ki-Nam Kim

发明人： Won-Suk Yang ,  Sang-Ho Song ,  Hong-Sik Jeong ,  Ki-Nam Kim

IPC分类号： H01L2348

CPC分类号： H01L21/76834 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76832 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894

摘要： An etch-stop layer is selectively provided between layers of a multiple-layered circuit in a selective manner so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer. In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense configurations.

摘要翻译： 选择性地在多层电路的层之间选择性地提供蚀刻停止层，以便允许随后的制造过程中的杂质脱气。 蚀刻停止层形成在下面的螺柱上，以便在形成在上层中的上覆螺柱的形成期间用作对准目标。 以这种方式，可以以相对致密的配置制造多层电路，例如存储器件。

公开(公告)号：US06812572B2

公开(公告)日：2004-11-02

申请号：US10442407

申请日：2003-05-21

申请人： Won-Suk Yang ,  Sang-Ho Song ,  Hong-Sik Jeong ,  Ki-Nam Kim

发明人： Won-Suk Yang ,  Sang-Ho Song ,  Hong-Sik Jeong ,  Ki-Nam Kim

IPC分类号： H01L2348

CPC分类号： H01L21/76834 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76832 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894

摘要： An etch-stop layer is selectively provided between layers of a multiple-layered circuit in a selective manner so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer. In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense configurations.

摘要翻译： 选择性地在多层电路的层之间选择性地提供蚀刻停止层，以便允许随后的制造过程中的杂质脱气。 蚀刻停止层形成在下面的螺柱上，以便在形成在上层中的上覆螺柱的形成期间用作对准目标。 以这种方式，可以以相对致密的配置制造多层电路，例如存储器件。

公开(公告)号：US06828617B2

公开(公告)日：2004-12-07

申请号：US10142773

申请日：2002-05-13

申请人： Hyung-Soo Uh ,  Sang-Ho Song ,  Ki-Nam Kim

发明人： Hyung-Soo Uh ,  Sang-Ho Song ,  Ki-Nam Kim

IPC分类号： H01L2976

CPC分类号： H01L27/10855 ,  H01L27/10894 ,  H01L28/60 ,  H01L28/90

摘要： A method for fabricating a capacitor of a semiconductor device, and a capacitor made in accordance with the method, wherein the method includes forming a plate electrode polysilicon layer on a semiconductor substrate having a cell array region and a core/peripheral circuit region. The plate electrode polysilicon layer in the cell array region is patterned to form an opening, wherein the inner wall of the opening is used as a plate electrode. After forming a dielectric layer in the opening, a storage node is formed as a spacer on the dielectric layer on the inner wall of the opening. The plate electrode polysilicon layer in the core/peripheral circuit region remains to provide the same height between the cell array region where the cell capacitor is formed and the core/peripheral circuit region.

摘要翻译： 一种制造半导体器件的电容器的方法和根据该方法制造的电容器，其中该方法包括在具有单元阵列区域和核心/外围电路区域的半导体衬底上形成平板电极多晶硅层。 将单元阵列区域中的平板电极多晶硅层图案化以形成开口，其中开口的内壁用作平板电极。 在开口中形成电介质层之后，在开口的内壁上的电介质层上形成作为间隔物的存储节点。 芯/外围电路区域中的平板电极多晶硅层保持为在形成单元电容器的单元阵列区域和核心/外围电路区域之间提供相同的高度。

公开(公告)号：US06670663B2

公开(公告)日：2003-12-30

申请号：US10233535

申请日：2002-09-04

申请人： Yoo-Sang Hwang ,  Sang-Ho Song ,  Byung Jun Park ,  Tae Young Chung

发明人： Yoo-Sang Hwang ,  Sang-Ho Song ,  Byung Jun Park ,  Tae Young Chung

IPC分类号： H01L27108

CPC分类号： H01L27/10852 ,  H01L21/76895 ,  H01L27/10897 ,  H01L28/82 ,  H01L28/91

摘要： A method for manufacturing a cell capacitor includes a step of forming an upper electrode and a trench for the lower electrode simultaneously in a single mask step. Further steps for manufacturing a cell capacitor includes forming a storage node contact by employing a predefined plate silicon layer and forming a capacitor dielectric using the storage contact node, as a result, it becomes possible to resolve “lift-off” problems, twin-bit failures, and misalignment.

公开(公告)号：US07553748B2

公开(公告)日：2009-06-30

申请号：US11463812

申请日：2006-08-10

申请人： Sung-Ho Jang ,  Sang-Ho Song ,  Sung-Sam Lee ,  Min-Sung Kang ,  Won-Tae Park ,  Min-Young Shim

发明人： Sung-Ho Jang ,  Sang-Ho Song ,  Sung-Sam Lee ,  Min-Sung Kang ,  Won-Tae Park ,  Min-Young Shim

IPC分类号： H01L21/20

CPC分类号： H01L21/76897 ,  H01L27/10876 ,  H01L29/7834

摘要： According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to form a semiconductor device. A spacer is formed on a surface of the gate structure. An insulating interlayer pattern is formed on the substrate including the gate structure, and an opening is formed through the insulating interlayer pattern corresponding to an impurity region of the substrate. A conductive pattern is formed in the opening and a top surface thereof is higher than a top surface of the insulating interlayer pattern. Thus, an upper portion of the conductive pattern is protruded from the insulating interlayer pattern. A capping pattern is formed on the insulating interlayer pattern, and a sidewall of the protruded portion of the conductive pattern is covered with the capping pattern. Accordingly, the capping pattern compensates for a thickness reduction of the gate mask.

摘要翻译： 根据一个实施例，在衬底的沟道区上形成包括栅极绝缘图案，栅极图案和栅极掩模的栅极结构，以形成半导体器件。 在栅极结构的表面上形成间隔物。 在包括栅极结构的基板上形成绝缘层间图案，并且通过与基板的杂质区域对应的绝缘层间图案形成开口。 在开口中形成导电图案，其顶表面高于绝缘层间图案的顶表面。 因此，导电图案的上部从绝缘层间图案突出。 在绝缘层间图案上形成封盖图案，并且用封盖图案覆盖导电图案的突出部分的侧壁。 因此，封盖图案补偿了栅极掩模的厚度减小。

公开(公告)号：US20070042583A1

公开(公告)日：2007-02-22

申请号：US11463812

申请日：2006-08-10

申请人： Sung-Ho JANG ,  Sang-Ho SONG ,  Sung-Sam LEE ,  Min-Sung KANG ,  Won-Tae PARK ,  Min-Young SHIM

发明人： Sung-Ho JANG ,  Sang-Ho SONG ,  Sung-Sam LEE ,  Min-Sung KANG ,  Won-Tae PARK ,  Min-Young SHIM

IPC分类号： H01L21/3205

CPC分类号： H01L21/76897 ,  H01L27/10876 ,  H01L29/7834

摘要： According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to form a semiconductor device. A spacer is formed on a surface of the gate structure. An insulating interlayer pattern is formed on the substrate including the gate structure, and an opening is formed through the insulating interlayer pattern corresponding to an impurity region of the substrate. A conductive pattern is formed in the opening and a top surface thereof is higher than a top surface of the insulating interlayer pattern. Thus, an upper portion of the conductive pattern is protruded from the insulating interlayer pattern. A capping pattern is formed on the insulating interlayer pattern, and a sidewall of the protruded portion of the conductive pattern is covered with the capping pattern. Accordingly, the capping pattern compensates for a thickness reduction of the gate mask.

摘要翻译： 根据一个实施例，在衬底的沟道区上形成包括栅极绝缘图案，栅极图案和栅极掩模的栅极结构，以形成半导体器件。 在栅极结构的表面上形成间隔物。 在包括栅极结构的基板上形成绝缘层间图案，并且通过与基板的杂质区域对应的绝缘层间图案形成开口。 在开口中形成导电图案，其顶表面高于绝缘层间图案的顶表面。 因此，导电图案的上部从绝缘层间图案突出。 在绝缘层间图案上形成封盖图案，并且用封盖图案覆盖导电图案的突出部分的侧壁。 因此，封盖图案补偿了栅极掩模的厚度减小。

公开(公告)号：US06479343B1

公开(公告)日：2002-11-12

申请号：US09510247

申请日：2000-02-22

申请人： Yoo-Sang Hwang ,  Sang-Ho Song ,  Byung Jun Park ,  Tae Young Chung

发明人： Yoo-Sang Hwang ,  Sang-Ho Song ,  Byung Jun Park ,  Tae Young Chung

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L21/76895 ,  H01L27/10897 ,  H01L28/82 ,  H01L28/91

摘要： A method for manufacturing a cell capacitor includes a step of forming an upper electrode and a trench for the lower electrode simultaneously in a single mask step. Further steps for manufacturing a cell capacitor includes forming a storage node contact by employing a predefined plate silicon layer and forming a capacitor dielectric using the storage contact node, as a result, it becomes possible to resolve “lift-off” problems, twin-bit failures, and misalignment.

摘要翻译： 电容器电容器的制造方法包括在单个掩模步骤中同时形成用于下电极的上电极和沟槽的步骤。 用于制造电池电容器的其它步骤包括通过采用预定义的硅板形成存储节点接触并且使用存储接触节点形成电容器电介质，结果，可以解决“剥离”问题，双位 失败和失调。

公开(公告)号：US06391736B1

公开(公告)日：2002-05-21

申请号：US09704763

申请日：2000-11-03

申请人： Hyung-Soo Uh ,  Sang-Ho Song ,  Ki-Nam Kim

发明人： Hyung-Soo Uh ,  Sang-Ho Song ,  Ki-Nam Kim

IPC分类号： H01L2120

CPC分类号： H01L27/10855 ,  H01L27/10894 ,  H01L28/60 ,  H01L28/90

摘要： A method for fabricating a capacitor of a semiconductor device, and a capacitor made in accordance with the method are disclosed. The method includes forming a plate electrode polysilicon layer on a semiconductor substrate having a cell array region and a core/peripheral circuit region. The plate electrode polysilicon layer in the cell array region is patterned to form an opening, wherein the inner wall of the opening is used as a plate electrode. After forming a dielectric layer in the opening, a storage node is formed as a spacer on the dielectric layer on the inner wall of the opening. The plate electrode polysilicon layer in the core/peripheral circuit region remains to provide the same height between the cell array region where the cell capacitor is formed and the core/peripheral circuit region.

摘要翻译： 公开了一种制造半导体器件的电容器的方法和根据该方法制成的电容器。 该方法包括在具有单元阵列区域和核心/外围电路区域的半导体衬底上形成平板电极多晶硅层。 将单元阵列区域中的平板电极多晶硅层图案化以形成开口，其中开口的内壁用作平板电极。 在开口中形成电介质层之后，在开口的内壁上的电介质层上形成作为间隔物的存储节点。 芯/外围电路区域中的平板电极多晶硅层保持为在形成单元电容器的单元阵列区域和核心/外围电路区域之间提供相同的高度。