公开(公告)号：US20130299770A1

公开(公告)日：2013-11-14

申请号：US13595324

申请日：2012-08-27

Applicant: Sung-Joon YOON ,  Hyung-Dong LEE

Inventor： Sung-Joon YOON ,  Hyung-Dong LEE

IPC: H01L45/00

CPC classification number: H01L45/146 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233

Abstract: A resistive memory device includes: a memory cell comprising first and second electrodes and a resistive layer formed therebetween, wherein the resistive layer is formed of a resistance change material; and a strained film formed adjacent to the resistive layer and configured to apply a strain to the resistive layer.

Abstract translation: 电阻式存储器件包括：存储单元，包括第一和第二电极以及在其间形成的电阻层，其中所述电阻层由电阻变化材料形成; 以及形成在所述电阻层附近并被配置为向所述电阻层施加应变的应变膜。

公开(公告)号：US20130246867A1

公开(公告)日：2013-09-19

申请号：US13603597

申请日：2012-09-05

Applicant: Hyung-Gyun YANG ,  Hyung-Dong LEE ,  Yong-Kee KWON ,  Young-Suk MOON ,  Hong-Sik KIM

Inventor： Hyung-Gyun YANG ,  Hyung-Dong LEE ,  Yong-Kee KWON ,  Young-Suk MOON ,  Hong-Sik KIM

IPC: G11C29/10 ,  G06F11/263

CPC classification number: G11C29/56 ,  G11C2029/5606

Abstract: This technology relates to smoothly performing a test on a memory circuit having a high memory capacity while reducing the size of a test circuit. A test circuit according to the present invention includes a test execution unit configured to perform a test on a target test memory circuit, an internal storage unit configured to store data for the test execution unit, and a conversion setting unit configured to set a part of or the entire storage space of the target test memory circuit as an external storage unit for storing the data for the test execution unit.

Abstract translation: 该技术涉及在减小测试电路的尺寸的同时平滑地对具有高存储容量的存储器电路进行测试。 根据本发明的测试电路包括被配置为对目标测试存储器电路进行测试的测试执行单元，被配置为存储用于测试执行单元的数据的内部存储单元，以及转换设置单元， 或作为用于存储测试执行单元的数据的外部存储单元的目标测试存储器电路的整个存储空间。

公开(公告)号：US20090115505A1

公开(公告)日：2009-05-07

申请号：US12136454

申请日：2008-06-10

Applicant: Hyung-Dong LEE ,  Jun-Ho LEE ,  Dong-Hwee KIM ,  Hwa-Yong YANG

Inventor： Hyung-Dong LEE ,  Jun-Ho LEE ,  Dong-Hwee KIM ,  Hwa-Yong YANG

IPC: G05F1/46

CPC classification number: H03H1/00 ,  H01L23/5223 ,  H01L2924/0002 ,  H03H2001/0064 ,  H01L2924/00

Abstract: Semiconductor device with a controllable decoupling capacitor includes a decoupling capacitor connected between a power voltage terminal and a ground terminal and a switching unit configured to enable/disable the decoupling capacitor in response to a control signal. According to another aspect, a semiconductor device with a controllable decoupling capacitor includes multiple circuits, decoupling capacitors being connected in parallel to each of the circuits and switching units being configured to enable/disable the decoupling capacitors in response to control signals.

Abstract translation: 具有可控去耦电容器的半导体器件包括连接在电源电压端子和接地端子之间的去耦电容器以及被配置为响应于控制信号使能/禁用去耦电容器的开关单元。 根据另一方面，具有可控解耦电容器的半导体器件包括多个电路，去耦电容器并联连接到每个电路，并且开关单元被配置为响应于控制信号启用/禁用去耦电容器。

公开(公告)号：US20100264945A1

公开(公告)日：2010-10-21

申请号：US12829994

申请日：2010-07-02

Applicant: Hyung-Dong LEE

Inventor： Hyung-Dong LEE

IPC: G01R31/02

CPC classification number: G11C29/02 ,  G11C7/08 ,  G11C29/022 ,  G11C29/023 ,  G11C29/50012 ,  G11C2029/4402

Abstract: A semiconductor integrated circuit includes a sense amplifier for sensing input data and a sense amplifier controller for blocking a signal path between the sense amplifier and a memory cell when a test mode signal is activated.

Abstract translation: 半导体集成电路包括用于感测输入数据的读出放大器和用于在测试模式信号被激活时阻塞读出放大器与存储单元之间的信号路径的读出放大器控制器。