公开(公告)号：US08559255B2

公开(公告)日：2013-10-15

申请号：US13569442

申请日：2012-08-08

申请人： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

发明人： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

IPC分类号： G11C7/00

CPC分类号： G11C16/3418 ,  G11C16/0416 ,  G11C16/24 ,  G11C16/3427

摘要： A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

摘要翻译： 提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。 在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。 可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。 该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。 这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

公开(公告)号：US08264898B2

公开(公告)日：2012-09-11

申请号：US13156763

申请日：2011-06-09

申请人： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

发明人： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

IPC分类号： G11C7/00

CPC分类号： G11C16/3418 ,  G11C16/0416 ,  G11C16/24 ,  G11C16/3427

摘要： A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

摘要翻译： 提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。 在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。 可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。 该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。 这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

公开(公告)号：US20110235412A1

公开(公告)日：2011-09-29

申请号：US13156763

申请日：2011-06-09

申请人： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

发明人： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/0416 ,  G11C16/24 ,  G11C16/3427

摘要： A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

摘要翻译： 提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。 在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。 可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。 该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。 这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

公开(公告)号：US20100103732A1

公开(公告)日：2010-04-29

申请号：US12650118

申请日：2009-12-30

申请人： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

发明人： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3418 ,  G11C16/0416 ,  G11C16/24 ,  G11C16/3427

摘要： A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

摘要翻译： 提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。 在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。 可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。 该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。 这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

公开(公告)号：US07986562B2

公开(公告)日：2011-07-26

申请号：US12650118

申请日：2009-12-30

申请人： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

发明人： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

IPC分类号： G11C16/06

CPC分类号： G11C16/3418 ,  G11C16/0416 ,  G11C16/24 ,  G11C16/3427

摘要： A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

摘要翻译： 提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。 在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。 可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。 该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。 这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

公开(公告)号：US20090161462A1

公开(公告)日：2009-06-25

申请号：US11963508

申请日：2007-12-21

申请人： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

发明人： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

IPC分类号： G11C7/02

CPC分类号： G11C16/3418 ,  G11C16/0416 ,  G11C16/24 ,  G11C16/3427

摘要： A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

摘要翻译： 提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。 在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。 可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。 该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。 这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

公开(公告)号：US20120294103A1

公开(公告)日：2012-11-22

申请号：US13569442

申请日：2012-08-08

申请人： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

发明人： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

IPC分类号： G11C7/12

CPC分类号： G11C16/3418 ,  G11C16/0416 ,  G11C16/24 ,  G11C16/3427

摘要： A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

摘要翻译： 提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。 在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。 可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。 该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。 这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

公开(公告)号：US07679967B2

公开(公告)日：2010-03-16

申请号：US11963508

申请日：2007-12-21

申请人： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

发明人： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

IPC分类号： G11C16/06

CPC分类号： G11C16/3418 ,  G11C16/0416 ,  G11C16/24 ,  G11C16/3427

摘要： A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

摘要翻译： 提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。 在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。 可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。 该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。 这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

公开(公告)号：US07995386B2

公开(公告)日：2011-08-09

申请号：US12275663

申请日：2008-11-21

申请人： Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

发明人： Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/08 ,  G11C16/3427

摘要： Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.

摘要翻译： 提出了有助于将预定义的负栅极电压施加到与在读取或验证操作期间选择的存储器单元相关联的所选字线相邻的字线的系统，方法和设备，以便于减少相邻字线干扰。 存储器组件可以包括优化的操作部件，其可以至少部分地基于预定义的操作标准，将预定义的负栅极电压施加到与被选择用于读取或验证操作所选择的存储器单元相关联的所选字线相邻的字线上，以便减少 所选择的存储单元中的相邻字线干扰，以便减少电压阈值的移位并保持期望的操作窗口。 优化的操作组件可选地可以包括评估器组件，其可以便于确定施加到相邻字线的负栅极电压是否被调整以便于将相邻字线干扰降低到低于预定阈值量。

公开(公告)号：US20100128521A1

公开(公告)日：2010-05-27

申请号：US12275663

申请日：2008-11-21

申请人： Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

发明人： Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/08 ,  G11C16/3427

摘要： Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.

摘要翻译： 提出了有助于将预定义的负栅极电压施加到与在读取或验证操作期间选择的存储器单元相关联的所选字线相邻的字线的系统，方法和设备，以便于减少相邻字线干扰。 存储器组件可以包括优化的操作部件，其可以至少部分地基于预定义的操作标准，将预定义的负栅极电压施加到与被选择用于读取或验证操作所选择的存储器单元相关联的所选字线相邻的字线上，以便减少 所选择的存储单元中的相邻字线干扰，以便减少电压阈值的移位并保持期望的操作窗口。 优化的操作组件可选地可以包括评估器组件，其可以便于确定施加到相邻字线的负栅极电压是否被调整以便于将相邻字线干扰降低到低于预定阈值量。