公开(公告)号：US20080233693A1

公开(公告)日：2008-09-25

申请号：US12108304

申请日：2008-04-23

申请人： Sung-young Lee ,  Sung-min Kim ,  Sung-dae Suk ,  Eun-jung Yun

发明人： Sung-young Lee ,  Sung-min Kim ,  Sung-dae Suk ,  Eun-jung Yun

IPC分类号： H01L21/8238

CPC分类号： H01L21/823828 ,  H01L21/823807 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/78696

摘要： A complementary metal-oxide semiconductor (CMOS) device includes an NMOS thin body channel including a silicon epitaxial layer. An NMOS insulating layer is formed on a surface of the NMOS thin body channel and surrounds the NMOS thin body channel. An NMOS metal gate is formed on the NMOS insulating layer. The CMOS device further includes a p-channel metal-oxide semiconductor (PMOS) transistor including a PMOS thin body channel including a silicon epitaxial layer. A PMOS insulating layer is formed on a surface of and surrounds the PMOS thin body channel. A PMOS metal gate is formed on the PMOS insulating layer. The NMOS insulating layer includes a silicon oxide layer and the PMOS insulating layer includes an electron-trapping layer, the NMOS insulating layer includes a hole trapping dielectric layer and the PMOS insulating layer includes a silicon oxide layer, or the NMOS insulating layer includes a hole-trapping dielectric layer and the PMOS insulating layer includes an electron-trapping dielectric layer.

摘要翻译： 互补金属氧化物半导体（CMOS）器件包括具有硅外延层的NMOS薄体通道。 NMOS绝缘层形成在NMOS薄体通道的表面上并且包围NMOS薄体通道。 在NMOS绝缘层上形成NMOS金属栅极。 CMOS器件还包括包括具有硅外延层的PMOS薄体通道的p沟道金属氧化物半导体（PMOS）晶体管。 在PMOS薄体通道的表面上形成PMOS绝缘层。 在PMOS绝缘层上形成PMOS金属栅极。 所述NMOS绝缘层包括氧化硅层，所述PMOS绝缘层包括电子捕获层，所述NMOS绝缘层包括空穴俘获介电层，所述PMOS绝缘层包括氧化硅层，或所述NMOS绝缘层包括孔 电介质层和PMOS绝缘层包括电子俘获电介质层。

公开(公告)号：US07781290B2

公开(公告)日：2010-08-24

申请号：US12108304

申请日：2008-04-23

申请人： Sung-young Lee ,  Sung-min Kim ,  Sung-dae Suk ,  Eun-jung Yun

发明人： Sung-young Lee ,  Sung-min Kim ,  Sung-dae Suk ,  Eun-jung Yun

IPC分类号： H01L21/8238

CPC分类号： H01L21/823828 ,  H01L21/823807 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/78696

摘要： A complementary metal-oxide semiconductor (CMOS) device includes an NMOS thin body channel including a silicon epitaxial layer. An NMOS insulating layer is formed on a surface of the NMOS thin body channel and surrounds the NMOS thin body channel. An NMOS metal gate is formed on the NMOS insulating layer. The CMOS device further includes a p-channel metal-oxide semiconductor (PMOS) transistor including a PMOS thin body channel including a silicon epitaxial layer. A PMOS insulating layer is formed on a surface of and surrounds the PMOS thin body channel. A PMOS metal gate is formed on the PMOS insulating layer. The NMOS insulating layer includes a silicon oxide layer and the PMOS insulating layer includes an electron-trapping layer, the NMOS insulating layer includes a hole trapping dielectric layer and the PMOS insulating layer includes a silicon oxide layer, or the NMOS insulating layer includes a hole-trapping dielectric layer and the PMOS insulating layer includes an electron-trapping dielectric layer.

摘要翻译： 互补金属氧化物半导体（CMOS）器件包括具有硅外延层的NMOS薄体通道。 NMOS绝缘层形成在NMOS薄体通道的表面上并且包围NMOS薄体通道。 在NMOS绝缘层上形成NMOS金属栅极。 CMOS器件还包括包括具有硅外延层的PMOS薄体通道的p沟道金属氧化物半导体（PMOS）晶体管。 在PMOS薄体通道的表面上形成PMOS绝缘层。 在PMOS绝缘层上形成PMOS金属栅极。 所述NMOS绝缘层包括氧化硅层，所述PMOS绝缘层包括电子捕获层，所述NMOS绝缘层包括空穴俘获介电层，所述PMOS绝缘层包括氧化硅层，或所述NMOS绝缘层包括孔 电介质层和PMOS绝缘层包括电子俘获电介质层。

公开(公告)号：US20060125018A1

公开(公告)日：2006-06-15

申请号：US11247939

申请日：2005-10-11

申请人： Sung-young Lee ,  Sung-min Kim ,  Sung-dae Suk ,  Eun-jung Yun

发明人： Sung-young Lee ,  Sung-min Kim ,  Sung-dae Suk ,  Eun-jung Yun

IPC分类号： H01L29/94

CPC分类号： H01L21/823828 ,  H01L21/823807 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/78696

摘要： A complementary metal-oxide semiconductor (CMOS) device includes an NMOS thin body channel including a silicon epitaxial layer. An NMOS insulating layer is formed on a surface of the NMOS thin body channel and surrounds the NMOS thin body channel. An NMOS metal gate is formed on the NMOS insulating layer. The CMOS device further includes a p-channel metal-oxide semiconductor (PMOS) transistor including a PMOS thin body channel including a silicon epitaxial layer. A PMOS insulating layer is formed on a surface of and surrounds the PMOS thin body channel. A PMOS metal gate is formed on the PMOS insulating layer. The NMOS insulating layer includes a silicon oxide layer and the PMOS insulating layer includes an electron-trapping layer, the NMOS insulating layer includes a hole trapping dielectric layer and the PMOS insulating layer includes a silicon oxide layer, or the NMOS insulating layer includes a hole-trapping dielectric layer and the PMOS insulating layer includes an electron-trapping dielectric layer.

摘要翻译： 互补金属氧化物半导体（CMOS）器件包括具有硅外延层的NMOS薄体通道。 NMOS绝缘层形成在NMOS薄体通道的表面上并且包围NMOS薄体通道。 在NMOS绝缘层上形成NMOS金属栅极。 CMOS器件还包括包括具有硅外延层的PMOS薄体通道的p沟道金属氧化物半导体（PMOS）晶体管。 在PMOS薄体通道的表面上形成PMOS绝缘层。 在PMOS绝缘层上形成PMOS金属栅极。 所述NMOS绝缘层包括氧化硅层，所述PMOS绝缘层包括电子捕获层，所述NMOS绝缘层包括空穴俘获介电层，所述PMOS绝缘层包括氧化硅层，或所述NMOS绝缘层包括孔 电介质层和PMOS绝缘层包括电子俘获电介质层。

公开(公告)号：US07588977B2

公开(公告)日：2009-09-15

申请号：US11452066

申请日：2006-06-13

申请人： Sung-dae Suk ,  Sung-young Lee ,  Dong-won Kim ,  Sung-min Kim

发明人： Sung-dae Suk ,  Sung-young Lee ,  Dong-won Kim ,  Sung-min Kim

IPC分类号： H01L29/768

CPC分类号： H01L29/42392 ,  H01L29/0673 ,  H01L29/66484 ,  H01L29/7831

摘要： A method of fabricating a MOSFET provides a plurality of nanowire-shaped channels in a self-aligned manner. According to the method, a first material layer and a semiconductor layer are sequentially formed on a semiconductor substrate. A first mask layer pattern is formed on the semiconductor layer, and recess regions are formed using the first mask layer pattern as an etch mask. A first reduced mask layer pattern is formed, and a filling material layer is formed on the surface of the substrate. A pair of second mask layer patterns are formed, and a first opening is formed. Then, the filling material layer is etched to form a second opening, the exposed first material layer is removed to expose the semiconductor layer, and a gate insulation layer and a gate electrode layer enclosing the exposed semiconductor layer are formed.

摘要翻译： 制造MOSFET的方法以自对准方式提供多个纳米线状通道。 根据该方法，在半导体衬底上依次形成第一材料层和半导体层。 在半导体层上形成第一掩模层图案，并且使用第一掩模层图案作为蚀刻掩模形成凹陷区域。 形成第一缩小的掩模层图案，并且在基板的表面上形成填充材料层。 形成一对第二掩模层图案，形成第一开口。 然后，蚀刻填充材料层以形成第二开口，去除暴露的第一材料层以暴露半导体层，并且形成包围暴露的半导体层的栅极绝缘层和栅极电极层。

公开(公告)号：US07795687B2

公开(公告)日：2010-09-14

申请号：US12538222

申请日：2009-08-10

申请人： Sung-dae Suk ,  Sung-young Lee ,  Dong-won Kim ,  Sung-min Kim

发明人： Sung-dae Suk ,  Sung-young Lee ,  Dong-won Kim ,  Sung-min Kim

IPC分类号： H01L29/76

CPC分类号： H01L29/42392 ,  H01L29/0673 ,  H01L29/66484 ,  H01L29/7831

摘要： A method of fabricating a MOSFET provides a plurality of nanowire-shaped channels in a self-aligned manner. According to the method, a first material layer and a semiconductor layer are sequentially formed on a semiconductor substrate. A first mask layer pattern is formed on the semiconductor layer, and recess regions are formed using the first mask layer pattern as an etch mask. A first reduced mask layer pattern is formed, and a filling material layer is formed on the surface of the substrate. A pair of second mask layer patterns are formed, and a first opening is formed. Then, the filling material layer is etched to form a second opening, the exposed first material layer is removed to expose the semiconductor layer, and a gate insulation layer and a gate electrode layer enclosing the exposed semiconductor layer are formed.

摘要翻译： 制造MOSFET的方法以自对准方式提供多个纳米线状通道。 根据该方法，在半导体衬底上依次形成第一材料层和半导体层。 在半导体层上形成第一掩模层图案，并且使用第一掩模层图案作为蚀刻掩模形成凹陷区域。 形成第一缩小的掩模层图案，并且在基板的表面上形成填充材料层。 形成一对第二掩模层图案，形成第一开口。 然后，蚀刻填充材料层以形成第二开口，去除暴露的第一材料层以暴露半导体层，并且形成包围暴露的半导体层的栅极绝缘层和栅极电极层。

公开(公告)号：US20090294864A1

公开(公告)日：2009-12-03

申请号：US12538222

申请日：2009-08-10

申请人： Sung-dae Suk ,  Sung-young Lee ,  Dong-won Kim ,  Sung-min Kim

发明人： Sung-dae Suk ,  Sung-young Lee ,  Dong-won Kim ,  Sung-min Kim

IPC分类号： H01L29/78

CPC分类号： H01L29/42392 ,  H01L29/0673 ,  H01L29/66484 ,  H01L29/7831

摘要： A method of fabricating a MOSFET provides a plurality of nanowire-shaped channels in a self-aligned manner. According to the method, a first material layer and a semiconductor layer are sequentially formed on a semiconductor substrate. A first mask layer pattern is formed on the semiconductor layer, and recess regions are formed using the first mask layer pattern as an etch mask. A first reduced mask layer pattern is formed, and a filling material layer is formed on the surface of the substrate. A pair of second mask layer patterns are formed, and a first opening is formed. Then, the filling material layer is etched to form a second opening, the exposed first material layer is removed to expose the semiconductor layer, and a gate insulation layer and a gate electrode layer enclosing the exposed semiconductor layer are formed.

摘要翻译： 制造MOSFET的方法以自对准方式提供多个纳米线状通道。 根据该方法，在半导体衬底上依次形成第一材料层和半导体层。 在半导体层上形成第一掩模层图案，并且使用第一掩模层图案作为蚀刻掩模形成凹陷区域。 形成第一缩小的掩模层图案，并且在基板的表面上形成填充材料层。 形成一对第二掩模层图案，形成第一开口。 然后，蚀刻填充材料层以形成第二开口，去除暴露的第一材料层以暴露半导体层，并且形成包围暴露的半导体层的栅极绝缘层和栅极电极层。

公开(公告)号：US20070004124A1

公开(公告)日：2007-01-04

申请号：US11452066

申请日：2006-06-13

申请人： Sung-dae Suk ,  Sung-young Lee ,  Dong-won Kim ,  Sung-min Kim

发明人： Sung-dae Suk ,  Sung-young Lee ,  Dong-won Kim ,  Sung-min Kim

IPC分类号： H01L21/8244

CPC分类号： H01L29/42392 ,  H01L29/0673 ,  H01L29/66484 ,  H01L29/7831

摘要： A method of fabricating a MOSFET provides a plurality of nanowire-shaped channels in a self-aligned manner. According to the method, a first material layer and a semiconductor layer are sequentially formed on a semiconductor substrate. A first mask layer pattern is formed on the semiconductor layer, and recess regions are formed using the first mask layer pattern as an etch mask. A first reduced mask layer pattern is formed, and a filling material layer is formed on the surface of the substrate. A pair of second mask layer patterns are formed, and a first opening is formed. Then, the filling material layer is etched to form a second opening, the exposed first material layer is removed to expose the semiconductor layer, and a gate insulation layer and a gate electrode layer enclosing the exposed semiconductor layer are formed.

摘要翻译： 制造MOSFET的方法以自对准方式提供多个纳米线状通道。 根据该方法，在半导体衬底上依次形成第一材料层和半导体层。 在半导体层上形成第一掩模层图案，并且使用第一掩模层图案作为蚀刻掩模形成凹陷区域。 形成第一缩小的掩模层图案，并且在基板的表面上形成填充材料层。 形成一对第二掩模层图案，形成第一开口。 然后，蚀刻填充材料层以形成第二开口，去除暴露的第一材料层以暴露半导体层，并且形成包围暴露的半导体层的栅极绝缘层和栅极电极层。

公开(公告)号：US07402483B2

公开(公告)日：2008-07-22

申请号：US11190695

申请日：2005-07-26

申请人： Eun-jung Yun ,  Sung-min Kim ,  Sung-young Lee

发明人： Eun-jung Yun ,  Sung-min Kim ,  Sung-young Lee

IPC分类号： H01L21/8238

CPC分类号： H01L29/78696 ,  H01L29/42392 ,  H01L29/66772

摘要： A multi-bridge-channel MOSFET (MBCFET) may be formed by forming a stacked structure on a substrate that includes channel layers and interchannel layers interposed between the channel layers. Trenches are formed by selectively etching the stacked structure. The trenches run across the stacked structure parallel to each other and separate a first stacked portion including channel patterns and interchannel patterns from second stacked portions including channel and interchannel layers remaining on both sides of the first stacked portion. First source and drain regions are grown using selective epitaxial growth. The first source and drain regions fill the trenches and connect to second source and drain regions defined by the second stacked portions. Marginal sections of the interchannel patterns of the first stacked portion are selectively exposed. Through tunnels are formed by selectively removing the interchannel patterns of the first stacked portion beginning with the exposed marginal sections. The through tunnels are surrounded by the first source and drain regions and the channel patterns. A gate is formed along with a gate dielectric layer, the gate filling the through tunnels and extending onto the first stacked portion.

摘要翻译： 可以通过在包括沟道层和介于沟道层之间的沟道间层的衬底上形成层叠结构来形成多桥沟MOSFET（MBCFET）。 通过选择性地蚀刻堆叠结构形成沟槽。 沟槽横跨层叠结构彼此平行地延伸，并且将包括通道图案和沟道间图案的第一堆叠部分与第二堆叠部分分开，包括残留在第一堆叠部分两侧的通道和通道间层。 使用选择性外延生长生长第一源区和漏区。 第一源极和漏极区域填充沟槽并连接到由第二堆叠部分限定的第二源极和漏极区域。 选择性地暴露第一堆叠部分的通道间图案的边缘部分。 通过从暴露的边缘部分开始选择性地去除第一堆叠部分的通道间图案，形成通道。 穿通隧道被第一源极和漏极区域以及沟道图案包围。 栅极与栅极电介质层一起形成，栅极填充通孔并延伸到第一堆叠部分上。

公开(公告)号：US20070200178A1

公开(公告)日：2007-08-30

申请号：US11783518

申请日：2007-04-10

申请人： Eun-jung Yun ,  Sung-min Kim ,  Sung-young Lee

发明人： Eun-jung Yun ,  Sung-min Kim ,  Sung-young Lee

IPC分类号： H01L27/12

CPC分类号： H01L29/66553 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66484 ,  H01L29/7831

摘要： A gate-all-around (GAA) transistor device has a pair of pillars that include the source/drain regions, a channel region bridging the source/drain regions, and a gate electrode and gate oxide which surround the channel region. The pillars are formed by providing a mono-crystalline silicon substrate, etching the substrate to form a pair of spaced-apart trenches such that a wall of the mono-crystalline silicon stands between the trenches, filling the trenches with insulative material, implanting impurities into the wall of mono-crystalline silicon, and forming an opening in the wall such that portions of the wall remain as pillars. A sacrificial layer is formed at the bottom of the opening. Then, the channel region is formed atop the sacrificial layer between the pillars. The sacrificial layer is subsequently removed and the gate oxide and gate electrode are formed around the channel region. One or more sidewall spacers are used to establish the effective width of the channel region and/or minimize parasitic capacitance between the source/drain regions and gate electrode.

公开(公告)号：US07253060B2

公开(公告)日：2007-08-07

申请号：US11074711

申请日：2005-03-09

申请人： Eun-jung Yun ,  Sung-min Kim ,  Sung-young Lee

发明人： Eun-jung Yun ,  Sung-min Kim ,  Sung-young Lee

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/78696 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78654

摘要： A gate-all-around (GAA) transistor device has a pair of pillars that include the source/drain regions, a channel region bridging the source/drain regions, and a gate electrode and gate oxide which surround the channel region. The pillars are formed by providing a mono-crystalline silicon substrate, etching the substrate to form a pair of spaced-apart trenches such that a wall of the mono-crystalline silicon stands between the trenches, filling the trenches with insulative material, implanting impurities into the wall of mono-crystalline silicon, and forming an opening in the wall such that portions of the wall remain as pillars. A sacrificial layer is formed at the bottom of the opening. Then, the channel region is formed atop the sacrificial layer between the pillars. The sacrificial layer is subsequently removed and the gate oxide and gate electrode are formed around the channel region. One or more sidewall spacers are used to establish the effective width of the channel region and/or minimize parasitic capacitance between the source/drain regions and gate electrode.

摘要翻译： 栅极全能（GAA）晶体管器件具有一对支柱，其包括源极/漏极区域，桥接源极/漏极区域的沟道区域以及围绕沟道区域的栅极电极和栅极氧化物。 支柱通过提供单晶硅衬底形成，蚀刻衬底以形成一对隔开的沟槽，使得单晶硅的壁站立在沟槽之间，用绝缘材料填充沟槽，将杂质注入 单晶硅的壁，并且在壁中形成开口，使得壁的一部分保持为支柱。 牺牲层形成在开口的底部。 然后，通道区域形成在支柱之间的牺牲层的顶部。 随后去除牺牲层，并且在沟道区周围形成栅极氧化物和栅电极。 使用一个或多个侧壁间隔物来建立沟道区域的有效宽度和/或最小化源极/漏极区域和栅电极之间的寄生电容。