公开(公告)号：US20170018462A1

公开(公告)日：2017-01-19

申请号：US14801332

申请日：2015-07-16

申请人： Sung-Dae Suk ,  Kang-lll Seo

发明人： Sung-Dae Suk ,  Kang-lll Seo

IPC分类号： H01L21/8238 ,  H01L29/423 ,  H01L21/84 ,  H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L29/786

CPC分类号： H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

摘要： A semiconductor device is provided. A substrate includes a first region and a second region. A first wire pattern, extending in a first direction, is formed at a first height from the substrate of the first region. A second wire pattern, extending in a second direction, is formed at a second height from the substrate of the second region. The first height is different from the second height. A first gate electrode, surrounding the first wire pattern, extends in a third direction crossing the first direction. A second gate electrode, surrounding the second wire pattern, extends in a fourth direction crossing the second direction. A first gate insulation layer is formed along a circumference of the first wire pattern and a sidewall of the first gate electrode. A second gate insulation layer is formed along a circumference of the second wire pattern and a sidewall of the second gate electrode.

摘要翻译： 提供半导体器件。 衬底包括第一区域和第二区域。 沿着第一方向延伸的第一线图案形成在距离第一区域的基板的第一高度处。 沿着第二方向延伸的第二线图案形成在距离第二区域的基板的第二高度处。 第一高度与第二高度不同。 围绕第一线图案的第一栅电极沿与第一方向交叉的第三方向延伸。 围绕第二线图案的第二栅电极沿与第二方向交叉的第四方向延伸。 第一栅绝缘层沿着第一布线图案的周边和第一栅电极的侧壁形成。 第二栅极绝缘层沿着第二布线图案的周边和第二栅电极的侧壁形成。

公开(公告)号：US09171845B2

公开(公告)日：2015-10-27

申请号：US14698338

申请日：2015-04-28

申请人： Sung-Dae Suk ,  Changwoo Oh ,  Sungil Park

发明人： Sung-Dae Suk ,  Changwoo Oh ,  Sungil Park

IPC分类号： H01L31/119 ,  H01L27/092 ,  H01L27/088 ,  H01L21/8234

CPC分类号： H01L27/0924 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/0922

摘要： Semiconductor devices including a first transistor and a second transistor are integrated on a substrate. Each of the first and second transistors include a nano-sized active region including source and drain regions provided in respective end portions of the nano-sized active region and a channel forming region provided between the source and drain regions. The source and drain regions of the first transistor have the same conductivity type as those of the second transistor, and the second transistor has a threshold voltage lower than that of the first transistor. The channel forming region of the second transistor may include a homogeneously doped region, whose conductivity type is the same as the source and drain regions of the second transistor and is different from the channel forming region of the first transistor.

摘要翻译： 包括第一晶体管和第二晶体管的半导体器件集成在基板上。 第一和第二晶体管中的每一个包括纳米尺寸的有源区，其包括设置在纳米尺寸有源区的相应端部中的源极和漏极区以及设置在源极和漏极区之间的沟道形成区。 第一晶体管的源极和漏极区域具有与第二晶体管相同的导电类型，并且第二晶体管具有低于第一晶体管的阈值电压的阈值电压。 第二晶体管的沟道形成区域可以包括均匀掺杂区域，其导电类型与第二晶体管的源极和漏极区域相同，并且与第一晶体管的沟道形成区域不同。

公开(公告)号：US20150243664A1

公开(公告)日：2015-08-27

申请号：US14698338

申请日：2015-04-28

申请人： Sung-Dae SUK ,  Changwoo Oh ,  Sungil Park

发明人： Sung-Dae SUK ,  Changwoo Oh ,  Sungil Park

IPC分类号： H01L27/092

CPC分类号： H01L27/0924 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/0922

摘要： Semiconductor devices including a first transistor and a second transistor are integrated on a substrate. Each of the first and second transistors include a nano-sized active region including source and drain regions provided in respective end portions of the nano-sized active region and a channel forming region provided between the source and drain regions. The source and drain regions of the first transistor have the same conductivity type as those of the second transistor, and the second transistor has a threshold voltage lower than that of the first transistor. The channel forming region of the second transistor may include a homogeneously doped region, whose conductivity type is the same as the source and drain regions of the second transistor and is different from the channel forming region of the first transistor.

摘要翻译： 包括第一晶体管和第二晶体管的半导体器件集成在基板上。 第一和第二晶体管中的每一个包括纳米尺寸的有源区，其包括设置在纳米尺寸有源区的相应端部中的源极和漏极区以及设置在源极和漏极区之间的沟道形成区。 第一晶体管的源极和漏极区域具有与第二晶体管相同的导电类型，并且第二晶体管具有低于第一晶体管的阈值电压的阈值电压。 第二晶体管的沟道形成区域可以包括均匀掺杂区域，其导电类型与第二晶体管的源极和漏极区域相同，并且与第一晶体管的沟道形成区域不同。

公开(公告)号：US09048120B2

公开(公告)日：2015-06-02

申请号：US14088650

申请日：2013-11-25

申请人： Sung-Dae Suk ,  Changwoo Oh ,  Sungil Park

发明人： Sung-Dae Suk ,  Changwoo Oh ,  Sungil Park

IPC分类号： H01L31/119 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L27/0924 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/0922

摘要： Semiconductor devices including a first transistor and a second transistor are integrated on a substrate. Each of the first and second transistors include a nano-sized active region including source and drain regions provided in respective end portions of the nano-sized active region and a channel forming region provided between the source and drain regions. The source and drain regions of the first transistor have the same conductivity type as those of the second transistor, and the second transistor has a threshold voltage lower than that of the first transistor. The channel forming region of the second transistor may include a homogeneously doped region, whose conductivity type is the same as the source and drain regions of the second transistor and is different from the channel forming region of the first transistor.

公开(公告)号：US20110272738A1

公开(公告)日：2011-11-10

申请号：US13096324

申请日：2011-04-28

申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-won Kim ,  Sung-dae Suk

发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-won Kim ,  Sung-dae Suk

IPC分类号： H01L29/78

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

摘要： A semiconductor device may include a substrate, an active semiconductor region of the substrate, and a gate electrode. The active semiconductor region may include a channel region between first and second junction regions. The channel region may include a first semiconductor material, the first and second junction regions may include a second semiconductor material, and the first and second semiconductor materials may be different. The gate electrode may be on the channel region with portions of the first and second junction regions being free of the gate electrode.

摘要翻译： 半导体器件可以包括衬底，衬底的有源半导体区域和栅电极。 有源半导体区域可以包括在第一和第二连接区域之间的沟道区域。 沟道区可以包括第一半导体材料，第一和第二结区可以包括第二半导体材料，并且第一和第二半导体材料可以是不同的。 栅电极可以在沟道区上，其中第一和第二结区的部分没有栅电极。

公开(公告)号：US08008141B2

公开(公告)日：2011-08-30

申请号：US12503594

申请日：2009-07-15

申请人： Ming Li ,  Kyoung-hwan Yeo ,  Sung-min Kim ,  Sung-dae Suk ,  Dong-won Kim

发明人： Ming Li ,  Kyoung-hwan Yeo ,  Sung-min Kim ,  Sung-dae Suk ,  Dong-won Kim

IPC分类号： H01L21/8232

CPC分类号： H01L29/78696 ,  H01L29/1083 ,  H01L29/66787

摘要： A semiconductor device with multiple channels includes a semiconductor substrate and a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other. A partial insulation layer is disposed on the semiconductor substrate between the conductive regions. A channel layer in the form of at least two bridges contacts the partial insulation layer, the at least two bridges being spaced apart from each other in a first direction and connecting the conductive regions with each other in a second direction that is at an angle relative to the first direction. A gate insulation layer is on the channel layer, and a gate electrode layer on the gate insulation layer and surrounding a portion of the channel layer.

摘要翻译： 具有多个通道的半导体器件包括半导体衬底和在半导体衬底上彼此间隔开并具有彼此相对的侧壁的一对导电区域。 在导电区域之间的半导体衬底上设置有部分绝缘层。 至少两个桥的形式的沟道层接触部分绝缘层，所述至少两个桥在第一方向上彼此间隔开，并且在与第一方向相反的第二方向上将导电区彼此连接 到第一个方向。 栅极绝缘层在沟道层上，栅极电极层在栅极绝缘层上并围绕沟道层的一部分。

公开(公告)号：US20110079859A1

公开(公告)日：2011-04-07

申请号：US12950064

申请日：2010-11-19

申请人： Chang-Woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

发明人： Chang-Woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

IPC分类号： H01L29/78

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

摘要： A semiconductor device may include a substrate, an active semiconductor region of the substrate, and a gate electrode. The active semiconductor region may include a channel region between first and second junction regions. The channel region may include a first semiconductor material, the first and second junction regions may include a second semiconductor material, and the first and second semiconductor materials may be different. The gate electrode may be on the channel region with portions of the first and second junction regions being free of the gate electrode.

摘要翻译： 半导体器件可以包括衬底，衬底的有源半导体区域和栅电极。 有源半导体区域可以包括在第一和第二连接区域之间的沟道区域。 沟道区可以包括第一半导体材料，第一和第二结区可以包括第二半导体材料，并且第一和第二半导体材料可以是不同的。 栅电极可以在沟道区上，其中第一和第二结区的部分没有栅电极。

公开(公告)号：US08461653B2

公开(公告)日：2013-06-11

申请号：US13096324

申请日：2011-04-28

申请人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

发明人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

IPC分类号： H01L29/41

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

摘要： A semiconductor device may include a substrate, an active semiconductor region of the substrate, and a gate electrode. The active semiconductor region may include a channel region between first and second junction regions. The channel region may include a first semiconductor material, the first and second junction regions may include a second semiconductor material, and the first and second semiconductor materials may be different. The gate electrode may be on the channel region with portions of the first and second junction regions being free of the gate electrode.

摘要翻译： 半导体器件可以包括衬底，衬底的有源半导体区域和栅电极。 有源半导体区域可以包括在第一和第二连接区域之间的沟道区域。 沟道区可以包括第一半导体材料，第一和第二结区可以包括第二半导体材料，并且第一和第二半导体材料可以是不同的。 栅电极可以在沟道区上，其中第一和第二结区的部分没有栅电极。

公开(公告)号：US07952151B2

公开(公告)日：2011-05-31

申请号：US12950064

申请日：2010-11-19

申请人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

发明人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

IPC分类号： H01L29/41

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

摘要： A semiconductor device may include a substrate, an active semiconductor region of the substrate, and a gate electrode. The active semiconductor region may include a channel region between first and second junction regions. The channel region may include a first semiconductor material, the first and second junction regions may include a second semiconductor material, and the first and second semiconductor materials may be different. The gate electrode may be on the channel region with portions of the first and second junction regions being free of the gate electrode.

摘要翻译： 半导体器件可以包括衬底，衬底的有源半导体区域和栅电极。 有源半导体区域可以包括在第一和第二连接区域之间的沟道区域。 沟道区可以包括第一半导体材料，第一和第二结区可以包括第二半导体材料，并且第一和第二半导体材料可以是不同的。 栅电极可以在沟道区上，其中第一和第二结区的部分没有栅电极。

公开(公告)号：US07795687B2

公开(公告)日：2010-09-14

申请号：US12538222

申请日：2009-08-10

申请人： Sung-dae Suk ,  Sung-young Lee ,  Dong-won Kim ,  Sung-min Kim

发明人： Sung-dae Suk ,  Sung-young Lee ,  Dong-won Kim ,  Sung-min Kim

IPC分类号： H01L29/76

CPC分类号： H01L29/42392 ,  H01L29/0673 ,  H01L29/66484 ,  H01L29/7831

摘要： A method of fabricating a MOSFET provides a plurality of nanowire-shaped channels in a self-aligned manner. According to the method, a first material layer and a semiconductor layer are sequentially formed on a semiconductor substrate. A first mask layer pattern is formed on the semiconductor layer, and recess regions are formed using the first mask layer pattern as an etch mask. A first reduced mask layer pattern is formed, and a filling material layer is formed on the surface of the substrate. A pair of second mask layer patterns are formed, and a first opening is formed. Then, the filling material layer is etched to form a second opening, the exposed first material layer is removed to expose the semiconductor layer, and a gate insulation layer and a gate electrode layer enclosing the exposed semiconductor layer are formed.

摘要翻译： 制造MOSFET的方法以自对准方式提供多个纳米线状通道。 根据该方法，在半导体衬底上依次形成第一材料层和半导体层。 在半导体层上形成第一掩模层图案，并且使用第一掩模层图案作为蚀刻掩模形成凹陷区域。 形成第一缩小的掩模层图案，并且在基板的表面上形成填充材料层。 形成一对第二掩模层图案，形成第一开口。 然后，蚀刻填充材料层以形成第二开口，去除暴露的第一材料层以暴露半导体层，并且形成包围暴露的半导体层的栅极绝缘层和栅极电极层。