公开(公告)号：US12073156B2

公开(公告)日：2024-08-27

申请号：US17695712

申请日：2022-03-15

申请人： Synopsys, Inc.

发明人： Amit Jalota ,  Andrew Saunders ,  Aruna Kanagaraj ,  Douglas Chang ,  Eshwari Rajendran ,  Prashant Gupta ,  Rajeev Murgai ,  Soumitra Majumder ,  Vasiliki Chatzi ,  Balkrishna Ramchandra Rashingkar

IPC分类号： G06F30/30 ,  G06F30/31 ,  G06F30/32 ,  G06F30/392 ,  G06F30/398

CPC分类号： G06F30/31 ,  G06F30/32 ,  G06F30/392 ,  G06F30/398

摘要： A system determines physical design information along a logic hierarchy of a circuit design. The system accesses physical design metrics associated with different parts of a physical design of a circuit. The system accesses a logic design of the circuit comprising a hierarchy of logic blocks. The system determines the physical design metrics associated with one or more logic blocks of the hierarchy of the logic design based on a relation between the physical design and the logic design. The system configures a user interface to display the hierarchy of the logic design of the circuit along with the physical design metrics associated with the one or more logic blocks of the hierarchy. The system sends the configured user interface for display.

公开(公告)号：US20220300687A1

公开(公告)日：2022-09-22

申请号：US17695712

申请日：2022-03-15

申请人： Synopsys, Inc.

发明人： Amit Jalota ,  Andrew Saunders ,  Aruna Kanagaraj ,  Douglas Chang ,  Eshwari Rajendran ,  Prashant Gupta ,  Rajeev Murgai ,  Soumitra Majumder ,  Vasiliki Chatzi ,  Balkrishna Ramchandra Rashingkar

IPC分类号： G06F30/31 ,  G06F30/392 ,  G06F30/32

摘要： A system determines physical design information along a logic hierarchy of a circuit design. The system accesses physical design metrics associated with different parts of a physical design of a circuit. The system accesses a logic design of the circuit comprising a hierarchy of logic blocks. The system determines the physical design metrics associated with one or more logic blocks of the hierarchy of the logic design based on a relation between the physical design and the logic design. The system configures a user interface to display the hierarchy of the logic design of the circuit along with the physical design metrics associated with the one or more logic blocks of the hierarchy. The system sends the configured user interface for display.