MEASURING DEVICE DEFECT SENSITIZATION IN TRANSISTOR-LEVEL CIRCUITS

    公开(公告)号:US20240061035A1

    公开(公告)日:2024-02-22

    申请号:US18071080

    申请日:2022-11-29

    申请人: Synopsys, Inc.

    摘要: A method of determining defect sensitization includes parsing a netlist of a circuit design to determine a plurality of potential defects and partitioning the circuit design into a plurality of blocks. The method also includes generating a graph representing the circuit design and determining a transitive closure of the graph. The method further includes grouping the plurality of potential defects to produce a plurality of groups of potential defects and selecting a potential defect from each group of the plurality of groups to form a simulation group of potential defects. The method also includes simulating the circuit design by injecting, into the circuit design, every potential defect of the simulation group to produce a set of outputs of the plurality of blocks and determining a defect sensitization for the simulation group of potential defects based on the set of outputs of the plurality of blocks.