公开(公告)号：US09449138B2

公开(公告)日：2016-09-20

申请号：US14452368

申请日：2014-08-05

Applicant: Synopsys Taiwan Co., Ltd.

Inventor： Yingtsai Chang ,  Sweyyan Shei ,  Hung-Chun Chiu ,  Meng-Chyi Lin ,  Hwa Mao ,  Ming-Yang Wang ,  Yu-Chin Hsu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5027

Abstract: A system for emulating a circuit design is presented. The system includes a host workstation coupled by an emulation interface to a field programmable gate array (FPGA) configured to emulate and verify the circuit design when the host workstation is invoked to verify the circuit design. The emulation interface is configured to provide timing and control information for at least the verify. The system further includes a non-transitory computer readable storage medium including instructions, which when executed cause a computer to compile a portion of the circuit design and an associated verification module adapted to configure the FPGA. A compilation is performed in accordance with a description file.

Abstract translation: 提出了一种仿真电路设计的系统。 该系统包括通过仿真接口耦合到现场可编程门阵列（FPGA）的主机工作站，其被配置为当主机工作站被调用以验证电路设计时仿真和验证电路设计。 仿真接口被配置为提供用于至少验证的定时和控制信息。 该系统进一步包括非暂时性的计算机可读存储介质，其包括指令，当执行时，使得计算机编译电路设计的一部分以及适于配置FPGA的相关联的验证模块。 根据描述文件执行编译。

公开(公告)号：US20140351777A1

公开(公告)日：2014-11-27

申请号：US14452368

申请日：2014-08-05

Applicant: Synopsys Taiwan Co., Ltd.

Inventor： Yingtsai Chang ,  Sweyyan Shei ,  Hung-Chun Chiu ,  Meng-Chyi Lin ,  Hwa Mao ,  Ming-Yang Wang ,  Yu-Chin Hsu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5027

Abstract: A system for emulating a circuit design is presented. The system includes a host workstation coupled by an emulation interface to a field programmable gate array (FPGA) configured to emulate and verify the circuit design when the host workstation is invoked to verify the circuit design. The emulation interface is configured to provide timing and control information for at least the verify. The system further includes computer readable storage medium including instructions, which when executed cause a computer to compile a portion of the circuit design and an associated verification module adapted to configure the FPGA. The compilation is in accordance with a description file.

Abstract translation: 提出了一种仿真电路设计的系统。 该系统包括通过仿真接口耦合到现场可编程门阵列（FPGA）的主机工作站，其被配置为当主机工作站被调用以验证电路设计时仿真和验证电路设计。 仿真接口被配置为提供用于至少验证的定时和控制信息。 该系统还包括包括指令的计算机可读存储介质，当执行时，使计算机编译电路设计的一部分，以及适于配置FPGA的相关联的验证模块。 编译符合一个描述文件。