公开(公告)号：US20140351777A1

公开(公告)日：2014-11-27

申请号：US14452368

申请日：2014-08-05

Applicant: Synopsys Taiwan Co., Ltd.

Inventor： Yingtsai Chang ,  Sweyyan Shei ,  Hung-Chun Chiu ,  Meng-Chyi Lin ,  Hwa Mao ,  Ming-Yang Wang ,  Yu-Chin Hsu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5027

Abstract: A system for emulating a circuit design is presented. The system includes a host workstation coupled by an emulation interface to a field programmable gate array (FPGA) configured to emulate and verify the circuit design when the host workstation is invoked to verify the circuit design. The emulation interface is configured to provide timing and control information for at least the verify. The system further includes computer readable storage medium including instructions, which when executed cause a computer to compile a portion of the circuit design and an associated verification module adapted to configure the FPGA. The compilation is in accordance with a description file.

Abstract translation: 提出了一种仿真电路设计的系统。 该系统包括通过仿真接口耦合到现场可编程门阵列（FPGA）的主机工作站，其被配置为当主机工作站被调用以验证电路设计时仿真和验证电路设计。 仿真接口被配置为提供用于至少验证的定时和控制信息。 该系统还包括包括指令的计算机可读存储介质，当执行时，使计算机编译电路设计的一部分，以及适于配置FPGA的相关联的验证模块。 编译符合一个描述文件。

公开(公告)号：US08719762B2

公开(公告)日：2014-05-06

申请号：US13730543

申请日：2012-12-28

Applicant: Synopsys Taiwan Co., Ltd.

Inventor： Yingtsai Chang ,  Sweyyan Shei ,  Meng-Chyi Lin ,  Hwa Mao ,  Ming Yang Wang ,  Yuchin Hsu

IPC: G06F17/50

CPC classification number: G06F17/5027 ,  G06F8/20

Abstract: A custom prototyping board and a controller are integrated to form an emulation system for emulating a circuit design. The controller may be disposed on an adaptor board. The custom prototyping board is defined by a set of board description files which further define the FPGA device(s) used in the system as well as the wire connections among the FPGA devices and connectors on the custom prototyping board. The FPGA device(s) is configured in accordance with the partitioned circuit design. Each partitioned circuit in the FPGA device is associated with a verification module for communicating with the controller to control and probe the emulation. A host workstation may be used to link with the controller to support co-simulation or co-emulation of the circuit design.

Abstract translation: 集成定制原型板和控制器以形成用于仿真电路设计的仿真系统。 控制器可以设置在适配器板上。 定制原型板由一组板描述文件定义，进一步定义了系统中使用的FPGA器件，以及定制原型板上的FPGA器件和连接器之间的导线连接。 FPGA器件根据分区电路设计进行配置。 FPGA器件中的每个分割电路与用于与控制器通信以控制和探测仿真的验证模块相关联。 主机工作站可以用于与控制器链接以支持电路设计的协同仿真或协同仿真。

公开(公告)号：US09449138B2

公开(公告)日：2016-09-20

申请号：US14452368

申请日：2014-08-05

Applicant: Synopsys Taiwan Co., Ltd.

Inventor： Yingtsai Chang ,  Sweyyan Shei ,  Hung-Chun Chiu ,  Meng-Chyi Lin ,  Hwa Mao ,  Ming-Yang Wang ,  Yu-Chin Hsu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5027

Abstract: A system for emulating a circuit design is presented. The system includes a host workstation coupled by an emulation interface to a field programmable gate array (FPGA) configured to emulate and verify the circuit design when the host workstation is invoked to verify the circuit design. The emulation interface is configured to provide timing and control information for at least the verify. The system further includes a non-transitory computer readable storage medium including instructions, which when executed cause a computer to compile a portion of the circuit design and an associated verification module adapted to configure the FPGA. A compilation is performed in accordance with a description file.

Abstract translation: 提出了一种仿真电路设计的系统。 该系统包括通过仿真接口耦合到现场可编程门阵列（FPGA）的主机工作站，其被配置为当主机工作站被调用以验证电路设计时仿真和验证电路设计。 仿真接口被配置为提供用于至少验证的定时和控制信息。 该系统进一步包括非暂时性的计算机可读存储介质，其包括指令，当执行时，使得计算机编译电路设计的一部分以及适于配置FPGA的相关联的验证模块。 根据描述文件执行编译。

公开(公告)号：US09384313B2

公开(公告)日：2016-07-05

申请号：US14253784

申请日：2014-04-15

Applicant: Synopsys, Inc. ,  Synopsys Taiwan Co., Ltd.

Inventor： Hung Chun Chiu ,  Meng-Chyi Lin ,  Kuen-Yang Tsai ,  Sweyyan Shei ,  Hwa Mao ,  Yingtsai Chang

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F2217/14

Abstract: User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations is field programmable gate array (FPGA) devices. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.

Abstract translation: 用户的寄存器传输级别（RTL）设计进行分析和检测，以使感兴趣的信号得以保留，并且可以在合成后位于网表中。 然后，执行用户的RTL合成和设计分区的原始流程。 分析输出以定位感兴趣的信号。 锁存器有选择地插入到网表中，以确保在运行时可以访问信号值。 之后，执行位置和路由（P＆R）处理，分析输出以将信号名称与寄存器（触发器和锁存器）或存储器块相关联，位置是现场可编程门阵列（FPGA）器件。 建立并保存关联数据库以供运行时使用。 在运行期间，可以在工作站上提供软件组件，供用户查询与RTL分层信号名称对应的信号值。

公开(公告)号：US08839179B2

公开(公告)日：2014-09-16

申请号：US13856004

申请日：2013-04-03

Applicant: Synopsys Taiwan Co., Ltd.

Inventor： Yingtsai Chang ,  Sweyyan Shei ,  Hung-Chun Chiu ,  Meng-Chyi Lin ,  Hwa Mao ,  Ming Yang Wang ,  Yuchin Hsu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5027

Abstract: A test system for testing prototype designs includes a host workstation, multiple interface devices, and multiple prototype boards. The prototype boards include programmable devices which implement one or more partitions of a user design and an associated verification modules. The verification modules probe signals of the partitions and transmit the probed signals to the interface devices. The verification modules can also transmit output signals generated by one or more partitions on the prototype boards to the host workstation via the interface devices, and transmit input signals, which are received from the host workstation via the interface devices, to one or more partitions on the prototype boards.

Abstract translation: 用于测试原型设计的测试系统包括主机工作站，多个接口设备和多个原型板。 原型板包括实现用户设计的一个或多个分区和相关联的验证模块的可编程设备。 验证模块探测分区的信号，并将探测信号发送到接口设备。 验证模块还可以通过接口设备将原型板上的一个或多个分区产生的输出信号发送到主机工作站，并且通过接口设备将从主机工作站接收的输入信号发送到一个或多个分区上 原型板。

公开(公告)号：US20150294055A1

公开(公告)日：2015-10-15

申请号：US14253784

申请日：2014-04-15

Applicant: Synopsys, Inc. ,  Synopsys Taiwan Co., Ltd.

Inventor： Hung Chun Chiu ,  Meng-Chyi Lin ,  Kuen-Yang Tsai ,  Sweyyan Shei ,  Hwa Mao ,  Yingtsai Chang

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F2217/14

Abstract: User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations is field programmable gate array (FPGA) devices. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.

Abstract translation: 用户的寄存器传输级别（RTL）设计进行分析和检测，以使感兴趣的信号得以保留，并且可以在合成后位于网表中。 然后，执行用户的RTL合成和设计分区的原始流程。 分析输出以定位感兴趣的信号。 锁存器有选择地插入到网表中，以确保在运行时可以访问信号值。 之后，执行位置和路由（P＆R）处理，分析输出以将信号名称与寄存器（触发器和锁存器）或存储器块相关联，位置是现场可编程门阵列（FPGA）器件。 建立并保存关联数据库以供运行时使用。 在运行期间，可以在工作站上提供软件组件，供用户查询与RTL分层信号名称对应的信号值。

公开(公告)号：US20130227509A1

公开(公告)日：2013-08-29

申请号：US13856004

申请日：2013-04-03

Applicant: Synopsys Taiwan Co., Ltd.

Inventor： Yingtsai Chang ,  Sweyyan Shei ,  Hung-Chun Chiu ,  Meng-Chyi Lin ,  Hwa Mao ,  Ming Yang Wang ,  Yuchin Hsu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5027

Abstract: A test system for testing prototype designs includes a host workstation, multiple interface devices, and multiple prototype boards. The prototype boards include programmable devices which implement one or more partitions of a user design and an associated verification modules. The verification modules probe signals of the partitions and transmit the probed signals to the interface devices. The verification modules can also transmit output signals generated by one or more partitions on the prototype boards to the host workstation via the interface devices, and transmit input signals, which are received from the host workstation via the interface devices, to one or more partitions on the prototype boards.

Abstract translation: 用于测试原型设计的测试系统包括主机工作站，多个接口设备和多个原型板。 原型板包括实现用户设计的一个或多个分区和相关联的验证模块的可编程设备。 验证模块探测分区的信号，并将探测信号发送到接口设备。 验证模块还可以通过接口设备将原型板上的一个或多个分区产生的输出信号发送到主机工作站，并且经由接口设备将从主机工作站接收的输入信号发送到一个或多个分区上 原型板。

公开(公告)号：US20130117007A1

公开(公告)日：2013-05-09

申请号：US13730543

申请日：2012-12-28

Applicant: Synopsys Taiwan Co., LTD.

Inventor： Yingtsai Chang ,  Sweyyan Shei ,  Meng-Chyi Lin ,  Hwa Mao ,  Ming Yang Wang ,  Yuchin Hsu

IPC: G06F17/50

CPC classification number: G06F17/5027 ,  G06F8/20

Abstract: A custom prototyping board and a controller are integrated to form an emulation system for emulating a circuit design. The controller may be disposed on an adaptor board. The custom prototyping board is defined by a set of board description files which further define the FPGA device(s) used in the system as well as the wire connections among the FPGA devices and connectors on the custom prototyping board. The FPGA device(s) is configured in accordance with the partitioned circuit design. Each partitioned circuit in the FPGA device is associated with a verification module for communicating with the controller to control and probe the emulation. A host workstation may be used to link with the controller to support co-simulation or co-emulation of the circuit design.

Abstract translation: 集成定制原型板和控制器以形成用于仿真电路设计的仿真系统。 控制器可以设置在适配器板上。 定制原型板由一组板描述文件定义，进一步定义了系统中使用的FPGA器件以及定制原型板上的FPGA器件和连接器之间的导线连接。 FPGA器件根据分区电路设计进行配置。 FPGA器件中的每个分割电路与用于与控制器通信以控制和探测仿真的验证模块相关联。 主机工作站可以用于与控制器链接以支持电路设计的协同仿真或协同仿真。