公开(公告)号：US20210217446A1

公开(公告)日：2021-07-15

申请号：US17214560

申请日：2021-03-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jonathan Tsung-Yung CHANG ,  Cheng-Hung LEE ,  Chi-Ting CHENG ,  Hung-Jen LIAO ,  Jhon-Jhy LIAW ,  Yen-Huei CHEN

IPC: G11C5/02 ,  G11C5/14 ,  G11C7/10 ,  G11C7/12 ,  G11C11/417 ,  G11C7/22

Abstract: A device disclosed includes first and second rows of memory cells, a first data line, and a first continuous data line. The first and second rows of memory cells are arranged in a first sub-bank and a second sub-bank, separated from the first sub-bank, respectively. The first data line is arranged across the first sub-bank and coupled to a first memory cell in the first row of memory cells. The first continuous data line includes a first portion arranged across the first sub-bank and a second portion arranged across the second sub-bank. The first continuous data line is coupled to a second memory cell in the second row of memory cells. The first portion of the first continuous data line is disposed in a first metal layer. The first data line and the second portion of the first continuous data line are in a second metal layer.

公开(公告)号：US20190172501A1

公开(公告)日：2019-06-06

申请号：US16265886

申请日：2019-02-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jonathan Tsung-Yung CHANG ,  Cheng-Hung LEE ,  Chi-Ting CHENG ,  Hung-Jen LIAO ,  Jhon-Jhy LIAW ,  Yen-Huei CHEN

IPC: G11C5/02 ,  G11C11/417 ,  G11C7/22 ,  G11C7/12 ,  G11C5/14 ,  G11C7/10

CPC classification number: G11C5/02 ,  G11C5/025 ,  G11C5/14 ,  G11C7/10 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/22 ,  G11C11/417

Abstract: A device includes a memory array. The memory array includes a first sub-bank, a second sub-bank, a strap cell and a continuous data line. The strap cell is arranged between the first sub-bank and the second sub-bank. The continuous data line includes a first portion coupled to the first sub-bank and a second portion disposed across the second sub-bank. The first portion of the continuous data line and the second portion of the continuous data line are disposed at separate layers above the strap cell.

公开(公告)号：US20170162232A1

公开(公告)日：2017-06-08

申请号：US15438567

申请日：2017-02-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jonathan Tsung-Yung CHANG ,  Cheng-Hung LEE ,  Chi-Ting CHENG ,  Hung-Jen LIAO ,  Jhon-Jhy LIAW ,  Yen-Huei CHEN

IPC: G11C5/02 ,  G11C7/22 ,  G11C7/10 ,  G11C5/14

CPC classification number: G11C5/02 ,  G11C5/025 ,  G11C5/14 ,  G11C7/10 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/22 ,  G11C11/417

Abstract: A device includes a first strap cell, a first data line, and a second data line. The first strap cell is arranged between a first row of memory cells and a second row of memory cells in a memory array. A first portion of the first data line is configured to transmit data to or from a first memory cell in the first row of memory cells. The second data line and a second portion of the first data line are configured to transmit data to or from a second memory cell in the second row of memory cells.

公开(公告)号：US20200152242A1

公开(公告)日：2020-05-14

申请号：US16744076

申请日：2020-01-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jonathan Tsung-Yung CHANG ,  Cheng-Hung LEE ,  Chi-Ting CHENG ,  Hung-Jen LIAO ,  Jhon-Jhy LIAW ,  Yen-Huei CHEN

IPC: G11C5/02 ,  G11C7/22 ,  G11C7/10 ,  G11C11/417 ,  G11C7/12 ,  G11C5/14

Abstract: A device includes a memory array. The memory array includes a first sub-bank, a first strap cell coupled to the first sub-bank, and a first continuous data line. The first continuous data line includes a first portion and a second portion coupled to the first sub-bank via the first strap cell. The first portion of the first continuous data line is disposed above the first strap cell and the second portion of the first continuous data line is disposed above the first portion of the first continuous data line.

公开(公告)号：US20170076755A1

公开(公告)日：2017-03-16

申请号：US15153687

申请日：2016-05-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jonathan Tsung-Yung CHANG ,  Cheng-Hung LEE ,  Chi-Ting CHENG ,  Hung-Jen LIAO ,  Jhon-Jhy LIAW ,  Yen-Huei CHEN

IPC: G11C5/02 ,  G11C7/22 ,  G11C7/10 ,  G11C5/14

CPC classification number: G11C5/02 ,  G11C5/025 ,  G11C5/14 ,  G11C7/10 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/22 ,  G11C11/417

Abstract: A device includes a memory array, a first data line, and a second data line. The memory array includes a first strap cell, a first sub-bank, and a second sub-bank, in which the first strap cell is disposed between the first sub-bank and the second sub-bank. The first data line has a first portion and a second portion, in which the first portion of the first data line is disconnected from the second portion of the first data line, and the second portion of the first data line is configured to couple the first sub-bank to a first input/output (I/O) circuit. The second data line and the first portion of the first data line are configured to couple the second sub-bank to the first I/O circuit.

Abstract translation: 一种设备包括存储器阵列，第一数据线和第二数据线。 存储器阵列包括第一带单元，第一子库和第二子库，其中第一带单元设置在第一子库和第二子库之间。 第一数据线具有第一部分和第二部分，其中第一数据线的第一部分与第一数据线的第二部分断开，并且第一数据线的第二部分被配置为将第一数据线的第一部分耦合第一数据线 子行到第一个输入/输出（I / O）电路。 第二数据线和第一数据线的第一部分被配置为将第二子组耦合到第一I / O电路。