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    Method of testing wafer
    2.
    发明授权
    Method of testing wafer 有权

    公开(公告)号：US11430733B2

    公开(公告)日：2022-08-30

    申请号：US17078523

    申请日：2020-10-23

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Yen-Hsung Ho ,  Chia-Yi Tseng ,  Chih-Hsun Lin ,  Kun-Tsang Chuang ,  Yung-Lung Hsu

    IPC分类号： H01L21/66 ,  H01L23/528 ,  H01L23/544 ,  H01L29/40 ,  H01L23/522

    摘要： A method includes capturing an image of a wafer, the wafer comprising a first conductive contact over an active region of the wafer and a second conductive contact over a shallow trench isolation (STI) region abutting the active region; identifying a brightness of a first contact region in the captured image at which the first conductive contact is rendered; identifying a brightness of a second contact region in the captured image at which the second conductive contact is rendered; and in response to the identified brightness of the first contact region in the captured image being substantially the same as the identified brightness of the second contact region in the captured image, determining that the second conductive contact is shorted to the first conductive contact.

    Methods for Improving Interlayer Dielectric Layer Topography
    3.
    发明申请
    Methods for Improving Interlayer Dielectric Layer Topography 审中-公开

    公开(公告)号：US20200294862A1

    公开(公告)日：2020-09-17

    申请号：US16889381

    申请日：2020-06-01

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Kuan-Wei Su ,  Chun Yu Huang ,  Chih-Hsun Lin ,  Ping-Pang Hsieh

    IPC分类号： H01L21/8234 ,  H01L21/02 ,  H01L27/088 ,  H01L21/311

    摘要： Integrated circuit devices having improved interlayer dielectric (ILD) layer topography and methods of fabrication thereof are disclosed herein. An exemplary integrated circuit device includes a first gate structure having a first height disposed over a substrate in a first region and a second gate structure having a second height disposed over the substrate in a second region. The second height is less than the first height. A first contact etch stop layer is disposed over the first gate structure. A second contact etch stop layer disposed over the second gate structure. The first contact etch stop layer has a first thickness, the second contact etch stop layer has a second thickness, and the second thickness is greater than the first thickness. An interlayer dielectric layer is disposed over the first contact etch stop layer and the second contact etch stop layer. A difference between a first sum of the first height and the first thickness and a second sum of the second height and the second thickness is less than or equal to about 10%.

    Methods for improving interlayer dielectric layer topography
    4.
    发明授权
    Methods for improving interlayer dielectric layer topography 有权

    公开(公告)号：US10699960B2

    公开(公告)日：2020-06-30

    申请号：US16117241

    申请日：2018-08-30

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Kuan-Wei Su ,  Chun Yu Huang ,  Chih-Hsun Lin ,  Ping-Pang Hsieh

    IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L21/311

    摘要： Methods for improving interlayer dielectric (ILD) layer topography and resulting integrated circuit devices are disclosed herein. An exemplary method includes forming a first contact etch stop layer having a first thickness over a first region of a wafer, forming a second contact etch stop layer having a second thickness over a second region of the wafer, and forming an ILD layer over the first contact etch stop layer and the second contact etch stop layer. A first topography variation exists between the first region and the second region. The second thickness is different than the first thickness to achieve a second topography variation that is less than the first topography variation. The first topography variation can be caused by a height difference between a first gate structure disposed over the wafer in the first region and a second gate structure disposed over the wafer in the second region.

    Methods for improving interlayer dielectric layer topography
    6.
    发明授权
    Methods for improving interlayer dielectric layer topography 有权

    公开(公告)号：US11257719B2

    公开(公告)日：2022-02-22

    申请号：US16889381

    申请日：2020-06-01

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Kuan-Wei Su ,  Chun Yu Huang ,  Chih-Hsun Lin ,  Ping-Pang Hsieh

    IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/311

    摘要： Integrated circuit devices having improved interlayer dielectric (ILD) layer topography and methods of fabrication thereof are disclosed herein. An exemplary integrated circuit device includes a first gate structure having a first height disposed over a substrate in a first region and a second gate structure having a second height disposed over the substrate in a second region. The second height is less than the first height. A first contact etch stop layer is disposed over the first gate structure. A second contact etch stop layer disposed over the second gate structure. The first contact etch stop layer has a first thickness, the second contact etch stop layer has a second thickness, and the second thickness is greater than the first thickness. An interlayer dielectric layer is disposed over the first contact etch stop layer and the second contact etch stop layer. A difference between a first sum of the first height and the first thickness and a second sum of the second height and the second thickness is less than or equal to about 10%.