公开(公告)号：US20200294862A1

公开(公告)日：2020-09-17

申请号：US16889381

申请日：2020-06-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuan-Wei Su ,  Chun Yu Huang ,  Chih-Hsun Lin ,  Ping-Pang Hsieh

IPC分类号： H01L21/8234 ,  H01L21/02 ,  H01L27/088 ,  H01L21/311

摘要： Integrated circuit devices having improved interlayer dielectric (ILD) layer topography and methods of fabrication thereof are disclosed herein. An exemplary integrated circuit device includes a first gate structure having a first height disposed over a substrate in a first region and a second gate structure having a second height disposed over the substrate in a second region. The second height is less than the first height. A first contact etch stop layer is disposed over the first gate structure. A second contact etch stop layer disposed over the second gate structure. The first contact etch stop layer has a first thickness, the second contact etch stop layer has a second thickness, and the second thickness is greater than the first thickness. An interlayer dielectric layer is disposed over the first contact etch stop layer and the second contact etch stop layer. A difference between a first sum of the first height and the first thickness and a second sum of the second height and the second thickness is less than or equal to about 10%.

公开(公告)号：US10699960B2

公开(公告)日：2020-06-30

申请号：US16117241

申请日：2018-08-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuan-Wei Su ,  Chun Yu Huang ,  Chih-Hsun Lin ,  Ping-Pang Hsieh

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L21/311

摘要： Methods for improving interlayer dielectric (ILD) layer topography and resulting integrated circuit devices are disclosed herein. An exemplary method includes forming a first contact etch stop layer having a first thickness over a first region of a wafer, forming a second contact etch stop layer having a second thickness over a second region of the wafer, and forming an ILD layer over the first contact etch stop layer and the second contact etch stop layer. A first topography variation exists between the first region and the second region. The second thickness is different than the first thickness to achieve a second topography variation that is less than the first topography variation. The first topography variation can be caused by a height difference between a first gate structure disposed over the wafer in the first region and a second gate structure disposed over the wafer in the second region.

公开(公告)号：US11257719B2

公开(公告)日：2022-02-22

申请号：US16889381

申请日：2020-06-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuan-Wei Su ,  Chun Yu Huang ,  Chih-Hsun Lin ,  Ping-Pang Hsieh

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/311

摘要： Integrated circuit devices having improved interlayer dielectric (ILD) layer topography and methods of fabrication thereof are disclosed herein. An exemplary integrated circuit device includes a first gate structure having a first height disposed over a substrate in a first region and a second gate structure having a second height disposed over the substrate in a second region. The second height is less than the first height. A first contact etch stop layer is disposed over the first gate structure. A second contact etch stop layer disposed over the second gate structure. The first contact etch stop layer has a first thickness, the second contact etch stop layer has a second thickness, and the second thickness is greater than the first thickness. An interlayer dielectric layer is disposed over the first contact etch stop layer and the second contact etch stop layer. A difference between a first sum of the first height and the first thickness and a second sum of the second height and the second thickness is less than or equal to about 10%.

公开(公告)号：US10211214B2

公开(公告)日：2019-02-19

申请号：US15456820

申请日：2017-03-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Kuan-Wei Su ,  Yung-Lung Hsu ,  Chih-Hsun Lin ,  Kun-Tsang Chuang ,  Chiang-Ming Chuang ,  Chia-Yi Tseng

IPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L29/49 ,  H01L29/788 ,  H01L23/31 ,  H01L23/29 ,  H01L27/11526 ,  H01L29/423 ,  H01L29/66

摘要： A semiconductor device having semiconductor device having a multi-height structure is provided. The semiconductor device having a multi-height structure includes a silicon substrate. A first structure and a second structure are respectively disposed on the silicon substrate and connected to each other. A limiting block is disposed on the second structure and near an edge of the second structure beside the first structure. A bottom anti-reflection coating (BARC) layer blanketly covering the first structure, the second structure and the limiting block, in which the BARC layer comprises a low-viscosity material, and the BARC layer overlying the top surface of the second structure has an external surface substantially parallel to the top surface of the second structure. Control gates are disposed on the external surface of the BARC layer.

公开(公告)号：US10672777B2

公开(公告)日：2020-06-02

申请号：US16278208

申请日：2019-02-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Kuan-Wei Su ,  Yung-Lung Hsu ,  Chih-Hsun Lin ,  Kun-Tsang Chuang ,  Chiang-Ming Chuang ,  Chia-Yi Tseng

IPC分类号： H01L27/11521 ,  H01L29/49 ,  H01L29/788 ,  H01L23/31 ,  H01L23/29 ,  H01L27/11526 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11548

摘要： A method for manufacturing a semiconductor device having a multi-height structure is provided. The semiconductor device having a multi-height structure includes a silicon substrate. A first structure and a second structure are respectively formed on the silicon substrate and connected to each other. A limiting block is formed on the second structure and near an edge of the second structure beside the first structure. A bottom anti-reflection coating (BARC) layer is formed to blanketly cover the first structure, the second structure and the limiting block, in which the BARC layer includes a low-viscosity material, and the BARC layer overlying the top surface of the second structure has an external surface substantially parallel to the top surface of the second structure. Control gates are formed on the external surface of the BARC layer.

公开(公告)号：US20200006152A1

公开(公告)日：2020-01-02

申请号：US16117241

申请日：2018-08-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuan-Wei Su ,  Chun Yu Huang ,  Chih-Hsun Lin ,  Ping-Pang Hsieh

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L21/311

摘要： Methods for improving interlayer dielectric (ILD) layer topography and resulting integrated circuit devices are disclosed herein. An exemplary method includes forming a first contact etch stop layer having a first thickness over a first region of a wafer, forming a second contact etch stop layer having a second thickness over a second region of the wafer, and forming an ILD layer over the first contact etch stop layer and the second contact etch stop layer. A first topography variation exists between the first region and the second region. The second thickness is different than the first thickness to achieve a second topography variation that is less than the first topography variation. The first topography variation can be caused by a height difference between a first gate structure disposed over the wafer in the first region and a second gate structure disposed over the wafer in the second region.