公开(公告)号：US11011238B2

公开(公告)日：2021-05-18

申请号：US16204268

申请日：2018-11-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Manish Arora ,  Hung-Jen Liao ,  Yen-Huei Chen ,  Nikhil Puri ,  Yu-Hao Hsu

IPC: G11C16/06 ,  G11C16/24 ,  H01L27/11551 ,  G11C7/12 ,  G11C16/04 ,  G11C11/00 ,  H01L27/11524

Abstract: A write line circuit includes a power supply node configured to carry a power supply voltage level, a reference node configured to carry a reference voltage level, a first input node configured to receive a first data signal, a second input node configured to receive a second data signal, a third input node configured to receive a control signal, and an output node. The write line circuit is configured to, responsive to the first data signal, the second data signal, and the control signal, either output one of the power supply voltage level or the reference voltage level on the output node, or float the output node.

公开(公告)号：US12136460B2

公开(公告)日：2024-11-05

申请号：US18362549

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Manish Arora ,  Yen-Huei Chen ,  Hung-Jen Liao ,  Nikhil Puri ,  Yu-Hao Hsu

IPC: G11C16/24 ,  G11C7/12 ,  G11C11/00 ,  G11C16/04 ,  H10B41/20 ,  H10B41/35

Abstract: A memory circuit includes first and second memory segments coupled to first and second write lines, and first and second write line circuits coupled to the first and second write lines and configured to receive first and second data signals. The first and second data signals have complementary low and high logical states during a write operation to the first or second memory segment, and each of the first and second data signals has the low logical state during a masked write operation to the first or second memory segment. The first and second write line circuits output, to the first and second write lines, first and second write line signals responsive to the first and second data signals during the write operation and float the first and second data lines during the masked write operation.

公开(公告)号：US11798632B2

公开(公告)日：2023-10-24

申请号：US17313404

申请日：2021-05-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Manish Arora ,  Yen-Huei Chen ,  Hung-Jen Liao ,  Nikhil Puri ,  Yu-Hao Hsu

IPC: G11C16/24 ,  G11C7/12 ,  G11C16/04 ,  G11C11/00 ,  H10B41/20 ,  H10B41/35

CPC classification number: G11C16/24 ,  G11C7/12 ,  G11C11/005 ,  G11C16/0483 ,  H10B41/20 ,  H10B41/35

Abstract: A write line circuit includes a power supply node configured to carry a power supply voltage level, a reference node configured to carry a reference voltage level, an output node, first and second switching devices coupled in series between the output node and the power supply node, and a third switching device directly coupled to each of the output node and the reference node. The first switching device is configured to selectively couple the output node to the second switching device responsive to a first data signal, the second switching device is configured to selectively couple the first switching device to the power supply node responsive to a second data signal, and the third switching device is configured to selectively couple the output node to the reference node responsive to the first data signal.