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公开(公告)号：US20240062815A1
公开(公告)日：2024-02-22
申请号：US18448067
申请日：2023-08-10
发明人： Zheng-Jun LIN , Chung-Cheng CHOU , Pei-Ling TSENG
CPC分类号： G11C13/004 , G11C7/065 , G11C7/08 , G11C7/12 , G11C2013/0042
摘要： A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell. A precharger is configured to selectively precharge the sensing circuit to a predetermined precharge voltage
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公开(公告)号：US20230236929A1
公开(公告)日：2023-07-27
申请号：US18183679
申请日：2023-03-14
CPC分类号： G06F11/1068 , G11C7/1096 , H03K19/20
摘要： A semiconductor device includes an error correction code circuit and a register circuit. The error correction code circuit is configured to generate first data according to second data. The register circuit is configured to generate reset information according to a difference between the first data and the second data, for adjusting a memory cell associated with the second data. A method is also disclosed herein.
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公开(公告)号：US20230072287A1
公开(公告)日：2023-03-09
申请号：US18054359
申请日：2022-11-10
发明人： Chung-Cheng CHOU , Zheng-Jun LIN , Pei-Ling TSENG
IPC分类号： G11C13/00
摘要： A resistive random-access memory (RRAM) circuit includes an RRAM device configured to output a cell current responsive to a bit line voltage, and a current limiter including an input terminal coupled to the RRAM device, first and second parallel current paths configured to conduct the cell current between the input terminal and a reference voltage node, and an amplifier configured to generate a first signal responsive to a voltage level at the input terminal and a reference voltage level. Each of the first and second current paths includes a switching device configured to selectively conduct a portion of the cell current responsive to the first signal.
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公开(公告)号：US20210201994A1
公开(公告)日：2021-07-01
申请号：US17200416
申请日：2021-03-12
发明人： Chung-Cheng CHOU , Zheng-Jun LIN , Pei-Ling TSENG
IPC分类号： G11C13/00
摘要： A method of forming a filament in a resistive random-access memory (RRAM) device includes applying a cell voltage across a resistive layer of the RRAM device, detecting an increase in a current through the resistive layer generated in response to the applied cell voltage, and in response to detecting the increase in the current, using a first switching device to reduce the current through the resistive layer.
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公开(公告)号：US20230063758A1
公开(公告)日：2023-03-02
申请号：US17461532
申请日：2021-08-30
摘要： A semiconductor device includes a memory circuit, an error correction code circuit, a register circuit and a write circuit. The memory circuit is configured to output, in response to at least one address signal, first data associated with at least one memory cell in the memory circuit. The error correction code circuit is configured to convert the first data to second data and configured to generate error information when the first data is not identical to the second data. The register circuit is configured to output, based on the error information, reset information corresponding to the at least one address signal. The write circuit is configured to reset the at least one memory cell according to the reset information. A method is also disclosed herein.
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公开(公告)号：US20220336016A1
公开(公告)日：2022-10-20
申请号：US17856811
申请日：2022-07-01
发明人： Chung-Cheng CHOU , Hsu-Shun CHEN , Chien-An LAI , Pei-Ling TSENG , Zheng-Jun LIN
IPC分类号： G11C13/00
摘要： A memory circuit includes a bias voltage generator including a bias voltage node, an activation voltage generator including a resistive device, and a first amplifier, a drive circuit including a second amplifier including an input terminal coupled to the bias voltage node, and a resistive random-access memory (RRAM) array. The activation voltage generator and the first amplifier are configured to generate a portion of a bias voltage level on the bias voltage node based on a resistance of the resistive device, and the drive circuit is configured to output a drive voltage having the bias voltage level to the RRAM array.
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公开(公告)号：US20210174871A1
公开(公告)日：2021-06-10
申请号：US17179052
申请日：2021-02-18
发明人： Chung-Cheng CHOU , Chien-An LAI , Hsu-Shun CHEN , Zheng-Jun LIN , Pei-Ling TSENG
IPC分类号： G11C13/00
摘要： A memory circuit includes a bias voltage generator, a drive circuit, and a resistive random-access memory (RRAM) device. The bias voltage generator includes a first transistor configured to generate a voltage difference based on a first current and an activation voltage, and is configured to output the activation voltage and a bias voltage based on the voltage difference. The drive circuit is configured to receive the bias voltage and output a drive voltage having a voltage level based on the bias voltage, and the RRAM device is configured to receive the activation voltage and conduct a second current responsive to the drive voltage and the activation voltage.
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公开(公告)号：US20240331770A1
公开(公告)日：2024-10-03
申请号：US18743997
申请日：2024-06-14
发明人： Chung-Cheng CHOU , Hsu-Shun CHEN , Chien-An LAI , Pei-Ling TSENG , Zheng-Jun LIN
IPC分类号： G11C13/00
CPC分类号： G11C13/0038 , G11C13/003 , G11C13/004 , G11C13/0069
摘要： A memory circuit includes a bias voltage generator including a first node, a current source coupled between a first power supply node and the first node, and a first transistor and a first resistive device coupled in series between the first node and a power reference node. A drive circuit includes a second node, an amplifier including a first input terminal coupled to the first node and a second input terminal coupled to the second node, and a second transistor coupled between a second power supply node and the second node and including a gate coupled to an output terminal of the amplifier, and a resistive random-access memory (RRAM) device is coupled between the second node and the power reference node.
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公开(公告)号：US20240233820A1
公开(公告)日：2024-07-11
申请号：US18615521
申请日：2024-03-25
发明人： Chung-Cheng CHOU , Zheng-Jun LIN , Pei-Ling TSENG
IPC分类号： G11C13/00
CPC分类号： G11C13/0038 , G11C13/003 , G11C2213/15 , G11C2213/79
摘要： A resistive random-access memory (RRAM) circuit includes a current source configured to output a first current, a first n-type transistor including a first drain terminal configured to receive the first current, an RRAM device, second and third n-type transistors including respective second and third drain terminals coupled to an output terminal of the RRAM device, an amplifier including a non-inverting input coupled to the first drain terminal, an inverting input configured to receive a first reference voltage level, and an output coupled to a gate of each of the first through third n-type transistors, a fourth n-type transistor coupled between the second n-type transistor and a power supply reference node, and a comparator including a non-inverting input configured to receive a second reference voltage level, an inverting input coupled to each of the second and third drain terminals, and an output coupled to a gate of the fourth n-type transistor.
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