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公开(公告)号：US20240312501A1
公开(公告)日：2024-09-19
申请号：US18675770
申请日：2024-05-28
IPC分类号： G11C7/12 , G11C11/4074 , G11C11/4094 , G11C11/412 , G11C11/413 , G11C11/419
CPC分类号： G11C7/12 , G11C11/413 , G11C11/4074 , G11C11/4094 , G11C11/412 , G11C11/419
摘要： A memory circuit includes a control circuit, a memory cell column, first and second bit lines coupled to the memory cell column, a write circuit coupled to a first end of each of the first and second bit lines, and a switching circuit including a first NAND gate including an input terminal coupled to the control circuit, an input terminal coupled to the first bit line, and a first output terminal, a first PMOS transistor coupled between a power supply node and the first bit line and including a gate coupled to the first output terminal, a second NAND gate including an input terminal coupled to the control circuit, an input terminal coupled to the second bit line, and a second output terminal, and a second PMOS transistor coupled between the power supply node and the second bit line and including a gate coupled to the second output terminal.
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公开(公告)号：US20230154507A1
公开(公告)日：2023-05-18
申请号：US18153464
申请日：2023-01-12
IPC分类号： G11C7/12 , G11C11/413
CPC分类号： G11C7/12 , G11C11/413 , G11C11/4094
摘要： A circuit includes a memory cell column coupled to a bit line pair and a write circuit that alternately biases a first end of the bit lines toward power supply and reference voltage levels in a write operation. Each of first and second switching circuits at second ends of the bit lines includes first and second logic circuits, each including an input terminal coupled to a corresponding bit line, and first and second switching devices, each including a gate coupled to the corresponding logic circuit. The first logic circuit and switching device couple the corresponding bit line to a power supply node simultaneously with the write circuit biasing the corresponding bit line toward the power supply voltage level, and the second logic circuit and switching device couple the corresponding bit line to a reference node simultaneously with the write circuit biasing the corresponding bit line toward the reference voltage level.
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公开(公告)号：US20210090621A1
公开(公告)日：2021-03-25
申请号：US17109964
申请日：2020-12-02
IPC分类号： G11C7/12
摘要： A memory circuit includes a reference node configured to carry a reference voltage having a reference voltage level, a power supply node configured to carry a power supply voltage having a power supply voltage level, a bit line coupled with a plurality of memory cells, a write circuit configured to charge the bit line by driving a voltage level on the bit line toward the power supply voltage level with a first current, and a switching circuit coupled between the power supply node and the bit line. The switching circuit is configured to receive the voltage level on the bit line, and responsive to a difference between the voltage level received on the bit line and the power supply voltage level being less than or equal to a threshold value, drive the voltage level on the bit line toward the power supply voltage level with a second current.
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公开(公告)号：US20200176053A1
公开(公告)日：2020-06-04
申请号：US16780739
申请日：2020-02-03
IPC分类号： G11C11/419
摘要： A memory system includes a first array (of memory cells) and a second array (of write assist circuits) arranged into columns each including a bit line and a bit_bar line coupled to corresponding memory cells of the first array and a corresponding at least one write assist circuit of the second array, each write assist circuit including: latch and memory-adapted third and fourth NMOS transistors. The latch includes: memory-adapted first PMOS and first NMOS transistors connected in series between a power-supply voltage and a first node selectively connectable to a ground voltage; and memory-adapted second PMOS transistor and second NMOS transistors connected in series between the power-supply voltage and a second node selectively connectable to ground voltage. The third NMOS transistor is connected in series between the first node and ground voltage; and the fourth NMOS transistor connected in series between the second node and ground voltage.
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公开(公告)号：US20190304520A1
公开(公告)日：2019-10-03
申请号：US15938393
申请日：2018-03-28
IPC分类号： G11C7/12
摘要： A circuit includes a voltage node, a plurality of memory cells, a bit line coupled with the plurality of memory cells, and a switching circuit coupled between the voltage node and the bit line. The switching circuit is configured to couple the voltage node with the bit line responsive to a voltage level on the bit line.
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6.发明申请公开(公告)号：US20180301185A1
公开(公告)日：2018-10-18
申请号：US15949774
申请日：2018-04-10
IPC分类号： G11C11/419
摘要： A write assist circuit includes: a memory-adapted latch and memory-adapted third and fourth NMOS transistors. The latch includes: a memory-adapted first PMOS transistor and a memory-adapted first NMOS transistor connected in series between a power-supply voltage and a first node, the first node being selectively connectable to a ground voltage; and a memory-adapted second PMOS transistor and a memory-adapted second NMOS transistor connected in series between the power-supply voltage and the second node, the second node being selectively connectable to the ground voltage. The third NMOS transistor is connected in series between the first node and the ground voltage; and the fourth NMOS transistor connected in series between the second node and the ground voltage. A gate electrode of each of the third and fourth transistors is connected to a latch-enable signal-line thereby for controlling the memory-adapted latch.
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