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    SEMICONDUCTOR DEVICE INCLUDING DISTRIBUTED WRITE DRIVING ARRANGEMENT
    2.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING DISTRIBUTED WRITE DRIVING ARRANGEMENT 有权

    公开(公告)号：US20220366965A1

    公开(公告)日：2022-11-17

    申请号：US17816048

    申请日：2022-07-29

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Hidehiro FUJIWARA ,  Hung-Jen LIAO ,  Li-Wen WANG ,  Jonathan Tsung-Yung CHANG ,  Yen-Huei CHEN

    IPC分类号： G11C11/4094 ,  G11C7/12 ,  G11C11/4096 ,  G11C5/06 ,  G11C11/419 ,  H01L21/48 ,  H01L27/11

    摘要： A semiconductor memory device includes: a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; a column of segments, each segment including bit cells that are connected correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including a global write driver and local write drivers included correspondingly in the segments; and the global write driver including a first equalizer circuit, arranged in a switched-coupling between the LWB line and the LWB_bar line, and arranged in a control-coupling with respect to signals correspondingly on the GWB line and the GWB_bar line, and the global write driver and the local write drivers each including first inversion couplings (coupled in parallel between the GWB line and the LWB line) and second inversion couplings (coupled in parallel between the GWB_bar line and the LWB_bar line).

    MEMORY COMPUTATION CIRCUIT
    3.
    发明申请
    MEMORY COMPUTATION CIRCUIT 有权

    公开(公告)号：US20220328096A1

    公开(公告)日：2022-10-13

    申请号：US17808536

    申请日：2022-06-23

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Yen-Huei CHEN ,  Hidehiro FUJIWARA ,  Hung-Jen LIAO ,  Jonathan Tsung-Yung CHANG

    IPC分类号： G11C11/419 ,  G11C11/412 ,  G06N3/08 ,  G06F17/16

    摘要： A memory circuit includes a first memory array including first memory cells wherein a plurality of first word lines is coupled with a plurality of rows of first memory cells in a first segment of the first memory array, and a plurality of second word lines is coupled with the plurality of rows of first memory cells in a second segment of the first memory array. The memory circuit also includes a read circuit configured to retrieve data from the first memory cells of the first memory array and a computation circuit configured to perform a matrix computation by combining first data retrieved from the first memory cells of the first segment with second data retrieved from the first memory cells of the second segment.

    MEMORY DEVICE AND SYSTEM
    6.
    发明公开
    MEMORY DEVICE AND SYSTEM 审中-公开

    公开(公告)号：US20230326521A1

    公开(公告)日：2023-10-12

    申请号：US17716609

    申请日：2022-04-08

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Yu-Der CHIH ,  Yun-Sheng CHEN ,  Jonathan Tsung-Yung CHANG ,  Hsin-Yuan YU ,  Chrong Jung LIN ,  Ya-Chin KING

    IPC分类号： G11C11/54

    CPC分类号： G11C11/54

    摘要： A memory device includes a first active area, a first doped structure of a first doping type, a second active area, a first gate structure and a second doped structure of a second doping type different from the first doping type. The second active area is disposed between the first active area and the first doped structure. The first gate structure is disposed between the first active area and the second active area in a layout view, and configured to store a first bit with the first active area and the second active area. The second doped structure is coupled to the first gate structure and disposed between the first doped structure and the second active area. The second doped structure and the first doped structure are configured to receive a first signal corresponding to the first bit from the first gate structure.

    MEMORY MACRO AND METHOD OF OPERATING THE SAME
    9.
    发明申请
    MEMORY MACRO AND METHOD OF OPERATING THE SAME 有权

    公开(公告)号：US20210287726A1

    公开(公告)日：2021-09-16

    申请号：US17335866

    申请日：2021-06-01

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chien-Kuo SU ,  Chiting CHENG ,  Pankaj AGGARWAL ,  Yen-Huei CHEN ,  Cheng Hung LEE ,  Hung-Jen LIAO ,  Jonathan Tsung-Yung CHANG ,  Jhon Jhy LIAW

    IPC分类号： G11C7/12 ,  G11C7/22 ,  G11C11/419

    摘要： A memory macro includes a first memory cell array, a first tracking circuit, a first and a second transistor. The first memory cell array includes rows of memory cells and columns of memory cells. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first control signal, a second set of memory cells configured as a first set of pull-down cells responsive to a second control signal, and a first tracking bit line coupled to the first and second set of memory cells. The first set of pull-down cells or loading cells is configured to track a memory cell of the first memory cell array. The first and second transistor are coupled to the first tracking bit line, and configured to charge the first tracking bit line to a pre-charge voltage level responsive to a tracking enable signal.