公开(公告)号：US20170345821A1

公开(公告)日：2017-11-30

申请号：US15255370

申请日：2016-09-02

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shu Fang FU ,  Chi-Feng HUANG ,  Chia-Chung CHEN ,  Victor Chiang LIANG ,  Fu-Huan TSAI

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L21/8238 ,  H03K3/03

CPC分类号： H01L27/0886 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/1041 ,  H01L29/7835 ,  H01L29/785 ,  H03K3/0315

摘要： A semiconductor device includes a fin extending from a substrate, a first source/drain feature, a second source/drain feature, and a gate structure on the fin. A distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature.

公开(公告)号：US20160197138A1

公开(公告)日：2016-07-07

申请号：US15071725

申请日：2016-03-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Chung CHEN ,  Shu Fang FU ,  Chang-Sheng LIAO

IPC分类号： H01L49/02 ,  H01L27/06

CPC分类号： H01L28/87 ,  H01L27/0629 ,  H01L27/0805 ,  H01L28/88

摘要： A high voltage metal-oxide-metal (HV-MOM) layout includes a first conductive element. The first element includes a first leg extending in a first direction, a second leg connected to the first leg, the second leg extending in a second direction different from the first direction, and a third leg connected to the second leg, the third leg extending in a first direction. The HV-MOM layout further includes a second conductive element separated from the first conductive element by a space. The second conductive element includes a serpentine structure, wherein the serpentine structure is enclosed on at least three sides by the first conductive element. The HV-MOM layout further includes a dielectric material filling the space between the first conductive element and the second conductive element.

摘要翻译： 高压金属氧化物金属（HV-MOM）布局包括第一导电元件。 第一元件包括沿第一方向延伸的第一腿部，连接到第一腿部的第二腿部，第二腿部沿与第一方向不同的第二方向延伸，第三腿部连接到第二腿部，第三腿部延伸 在第一个方向。 HV-MOM布局还包括通过空间与第一导电元件分离的第二导电元件。 第二导电元件包括​​蛇形结构，其中蛇形结构被第一导电元件封闭在至少三个侧面上。 HV-MOM布局还包括填充第一导电元件和第二导电元件之间的空间的电介质材料。

公开(公告)号：US20150021676A1

公开(公告)日：2015-01-22

申请号：US13945435

申请日：2013-07-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Chung CHEN ,  Shu Fang FU ,  Chang-Sheng LIAO

IPC分类号： H01L27/06 ,  H01L27/108

CPC分类号： H01L28/87 ,  H01L27/0629 ,  H01L27/0805 ,  H01L28/88

摘要： A high voltage metal-oxide-metal (HV-MOM) device includes a substrate, a deep well in the substrate and at least one high voltage well in the substrate over the deep well. The HV-MOM device further includes a dielectric layer over each high voltage well of the at least one high voltage well and a gate structure over the dielectric layer. The HV-MOM device further includes an inter-layer dielectric (ILD) layer over the substrate, the ILD layer surrounding the gate structure. The HV-MOM device further includes a first inter-metal dielectric (IMD) layer over the ILD layer and a first metal feature in the first IMD layer, wherein the first metal feature is part of a MOM capacitor.

摘要翻译： 高压金属氧化物金属（HV-MOM）器件包括衬底，衬底中的深阱以及深井中衬底中的至少一个高电压阱。 所述HV-MOM器件还包括在所述至少一个高电压阱的每个高电压阱上的电介质层和在所述电介质层上的栅极结构。 HV-MOM器件还包括在衬底上的层间电介质（ILD）层，围绕栅极结构的ILD层。 HV-MOM器件还包括在ILD层上的第一金属介电层（IMD）层和第一IMD层中的第一金属特征，其中第一金属特征是MOM电容器的一部分。

公开(公告)号：US20230163125A1

公开(公告)日：2023-05-25

申请号：US18151990

申请日：2023-01-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shu Fang FU ,  Chi-Feng HUANG ,  Chia-Chung CHEN ,  Victor Chiang LIANG ,  Fu-Huan TSAI

IPC分类号： H01L27/088 ,  H01L27/02 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8238

CPC分类号： H01L27/0886 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/1041 ,  H01L27/0924 ,  H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/7835 ,  H01L21/823814 ,  H03K3/0315

摘要： A method of fabricating a semiconductor device includes forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip. The method further includes forming a first source/drain feature between the gate structure and the first edge structure. The method further includes forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature. The method further includes implanting a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.

公开(公告)号：US20200027878A1

公开(公告)日：2020-01-23

申请号：US16586273

申请日：2019-09-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shu Fang FU ,  Chi-Feng HUANG ,  Chia-Chung CHEN ,  Victor Chiang LIANG ,  Fu-Huan TSAI

IPC分类号： H01L27/088 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/02 ,  H01L27/092 ,  H01L29/10

摘要： A method includes forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip. The method includes forming a first source/drain feature between the gate structure and the first edge structure; and a second source/drain feature between the gate structure and the second edge structure. A distance between the gate structure and the first source/drain feature is from about 1.5 to about 4.5 times greater than a distance between the gate structure and the second source/drain feature. The method includes implanting a buried channel in the semiconductor strip. A top surface of the buried channel is spaced from a top surface of the semiconductor strip. A bottom surface of the buried channel is closer to the top surface of the semiconductor strip than a bottom surface of the first source/drain feature. A dopant concentration of the buried channel is highest under the gate structure.