公开(公告)号：US20210375862A1

公开(公告)日：2021-12-02

申请号：US17403732

申请日：2021-08-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Chung CHEN ,  Chi-Feng HUANG ,  Victor Chiang LIANG ,  Fu-Huan TSAI ,  Hsieh-Hung HSIEH ,  Tzu-Jin YEH ,  Han-Min TSAI ,  Hong-Lin CHU

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/167 ,  H01L29/10 ,  H01L29/423 ,  H01L29/417 ,  H03D7/14 ,  H01L29/66 ,  H01L29/78

摘要： A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

公开(公告)号：US20220367318A1

公开(公告)日：2022-11-17

申请号：US17874274

申请日：2022-07-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yang-Che CHEN ,  Chen-Hua LIN ,  Huang-Wen TSENG ,  Victor Chiang LIANG ,  Chwen-Ming LIU

IPC分类号： H01L23/373 ,  H01L23/00 ,  H01L23/367

摘要： A method includes forming a solder layer on a surface of one or more chips. A lid is positioned over the solder layer on each of the one or more chips. Heat and pressure are applied to melt the solder layer and attach each lid to a corresponding solder layer. The solder layer has a thermal conductivity of ≥50 W/mK.

公开(公告)号：US20190165678A1

公开(公告)日：2019-05-30

申请号：US15938482

申请日：2018-03-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chu Fu CHEN ,  Chi-Feng HUANG ,  Chia-Chung CHEN ,  Chin-Lung CHEN ,  Victor Chiang LIANG ,  Chia-Cheng PAO

IPC分类号： H02M3/158 ,  H01L29/423 ,  H01L29/08 ,  H01L29/80 ,  H01L21/84

摘要： A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region under the gate structure. The transistor further includes a source in the substrate adjacent a first side of the gate structure. The transistor further includes a drain in the substrate adjacent a second side of the gate structure, wherein the second side of the gate structure is opposite the first side of the gate structure. The transistor further includes a first lightly doped drain (LDD) region adjacent the source. The transistor further includes a second LDD region adjacent the drain. The transistor further includes a doping extension region adjacent the first LDD region.

公开(公告)号：US20170345821A1

公开(公告)日：2017-11-30

申请号：US15255370

申请日：2016-09-02

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shu Fang FU ,  Chi-Feng HUANG ,  Chia-Chung CHEN ,  Victor Chiang LIANG ,  Fu-Huan TSAI

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L21/8238 ,  H03K3/03

CPC分类号： H01L27/0886 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/1041 ,  H01L29/7835 ,  H01L29/785 ,  H03K3/0315

摘要： A semiconductor device includes a fin extending from a substrate, a first source/drain feature, a second source/drain feature, and a gate structure on the fin. A distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature.

公开(公告)号：US20230387182A1

公开(公告)日：2023-11-30

申请号：US18447482

申请日：2023-08-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Yu CHOU ,  Yang-Che CHEN ,  Chen-Hua LIN ,  Victor Chiang LIANG ,  Huang-Wen TSENG ,  Chwen-Ming LIU

IPC分类号： H01F41/34 ,  H01L23/522 ,  H01L27/08

CPC分类号： H01L28/10 ,  H01F41/34 ,  H01L23/5227 ,  H01L27/08

摘要： An inductive device includes an insulating layer, a lower magnetic layer, and an upper magnetic layer that are formed such that the insulating layer does not separate the lower magnetic layer and the upper magnetic layer at the outer edges or wings of the inductive device. The lower magnetic layer and the upper magnetic layer form a continuous magnetic layer around the insulating layer and the conductors of the inductive device. Magnetic leakage paths are provided by forming openings through the upper magnetic layer. The openings may be formed through the upper magnetic layer by semiconductor processes that have relatively higher precision and accuracy compared to semiconductor processes for forming the insulating layer such as spin coating. This reduces magnetic leakage path variation within the inductive device and from inductive device to inductive device.

公开(公告)号：US20220231116A1

公开(公告)日：2022-07-21

申请号：US17658266

申请日：2022-04-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Yu CHOU ,  Yang-Che CHEN ,  Chen-Hua LIN ,  Victor Chiang LIANG ,  Huang-Wen TSENG ,  Chwen-Ming LIU

IPC分类号： H01L49/02 ,  H01F41/34

摘要： An inductive device includes an insulating layer, a lower magnetic layer, and an upper magnetic layer that are formed such that the insulating layer does not separate the lower magnetic layer and the upper magnetic layer at the outer edges or wings of the inductive device. The lower magnetic layer and the upper magnetic layer form a continuous magnetic layer around the insulating layer and the conductors of the inductive device. Magnetic leakage paths are provided by forming openings through the upper magnetic layer. The openings may be formed through the upper magnetic layer by semiconductor processes that have relatively higher precision and accuracy compared to semiconductor processes for forming the insulating layer such as spin coating. This reduces magnetic leakage path variation within the inductive device and from inductive device to inductive device.

公开(公告)号：US20210028309A1

公开(公告)日：2021-01-28

申请号：US17027032

申请日：2020-09-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chu Fu CHEN ,  Chi-Feng HUANG ,  Chia-Chung CHEN ,  Chin-Lung CHEN ,  Victor Chiang LIANG ,  Chia-Cheng PAO

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H02M3/158

摘要： A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region. The transistor further includes a source/drain (S/D) in the substrate adjacent to the gate structure. The transistor further includes a lightly doped drain (LDD) region adjacent to the S/D, wherein a dopant concentration in the first LDD is less than a dopant concentration in the S/D. The transistor further includes a doping extension region adjacent the LDD region, wherein the doping extension region extends farther under the gate structure than the LDD region, and a maximum depth of the doping extension region is 10-times to 30-times greater than a maximum depth of the LDD.

公开(公告)号：US20200152676A1

公开(公告)日：2020-05-14

申请号：US16738887

申请日：2020-01-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Victor Chiang LIANG ,  Fu-Huan TSAI ,  Fang-Ting KUO ,  Meng-Chang HO ,  Yu-Lin WEI ,  Chi-Feng HUANG

IPC分类号： H01L27/146 ,  H01L29/66 ,  H01L27/07 ,  H01L29/93

摘要： A method of making a semiconductor device includes etching a substrate to define a trench in a substrate, wherein the trench is adjacent to an active region in the substrate, and etching the substrate includes patterning a mask. The method further includes partially removing the mask to expose a first portion of the active region, wherein the first portion extends a first distance from the trench. The method further includes depositing a dielectric material to fill the trench and cover the first portion of the active region. The method further includes removing the mask, wherein the removing of the mask includes maintaining the dielectric material covering the first portion of the active region. The method further includes forming a gate structure over the active region and over the dielectric material.

公开(公告)号：US20150108582A1

公开(公告)日：2015-04-23

申请号：US14310333

申请日：2014-06-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD

发明人： Chia-Chung CHEN ,  Chi-Feng HUANG ,  Victor Chiang LIANG

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/66795 ,  H01L21/26513 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/66787 ,  H01L29/785

摘要： A transistor includes a substrate having an upper surface, a fin structure protruding from the upper surface of the substrate, an isolation structure over the upper surface of the substrate and surrounding a lower portion of the fin structure, and a first doped region at least partially embedded in an upper portion of the fin structure. The fin structure extends along a first direction. The first doped region has a first type doping different from that of the fin structure.

摘要翻译： 晶体管包括具有上表面的衬底，从衬底的上表面突出的鳍结构，在衬底的上表面上并围绕鳍结构的下部的隔离结构，以及至少部分地形成第一掺杂区 嵌入翅片结构的上部。 翅片结构沿着第一方向延伸。 第一掺杂区具有不同于鳍结构的第一掺杂区。

公开(公告)号：US20240312851A1

公开(公告)日：2024-09-19

申请号：US18671330

申请日：2024-05-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yang-Che CHEN ,  Chen-Hua LIN ,  Huang-Wen TSENG ,  Victor Chiang LIANG ,  Chwen-Ming LIU

IPC分类号： H01L23/04 ,  H01L21/52 ,  H01L21/60 ,  H01L23/00 ,  H01L23/06 ,  H01L23/14 ,  H01L23/498

CPC分类号： H01L23/04 ,  H01L21/52 ,  H01L23/06 ,  H01L23/14 ,  H01L23/49816 ,  H01L24/14 ,  H01L2021/60022

摘要： A semiconductor package includes a semiconductor chip disposed over a first main surface of a first substrate, a package lid disposed over the semiconductor chip, and spacers extending from the package lid through corresponding holes in the first substrate. The spacers enter the holes at a first main surface of the first substrate and extend beyond an opposing second main surface of the first substrate.