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    SEMICONDUCTOR PACKAGE FOR HIGH-SPEED DATA TRANSMISSION AND MANUFACTURING METHOD THEREOF
    1.
    发明申请
    SEMICONDUCTOR PACKAGE FOR HIGH-SPEED DATA TRANSMISSION AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20220336384A1

    公开(公告)日：2022-10-20

    申请号：US17809903

    申请日：2022-06-30

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： HUAN-NENG CHEN ,  WEN-SHIANG LIAO

    IPC分类号： H01L23/66 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01P3/12 ,  H01L23/498 ,  H01L25/00

    摘要： A semiconductor structure includes: a substrate; a first dielectric layer over the substrate; a waveguide over the first dielectric layer; a second dielectric layer over the first dielectric layer and laterally surrounding the waveguide; a first conductive member and a second conductive member over the second dielectric layer and the waveguide, the first conductive member and the second conductive member being in contact with the waveguide; a conductive bump on one side of the substrate and electrically connected to the first conductive member or the second conductive member; and a conductive via extending through the substrate and electrically connecting the conductive bump to the first conductive member or the second conductive member. The waveguide is configured to transmit an electromagnetic signal between the first conductive member and the second conductive member.

    SEMICONDUCTOR PACKAGE FOR HIGH-SPEED DATA TRANSMISSION AND MANUFACTURING METHOD THEREOF
    2.
    发明申请
    SEMICONDUCTOR PACKAGE FOR HIGH-SPEED DATA TRANSMISSION AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20230084445A1

    公开(公告)日：2023-03-16

    申请号：US18056264

    申请日：2022-11-17

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： HUAN-NENG CHEN ,  WEN-SHIANG LIAO

    IPC分类号： H01L23/66 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01P3/12 ,  H01L23/498 ,  H01L25/00

    摘要： A method of manufacturing the semiconductor structure includes: providing a substrate; forming a first conductive via and a second conductive via extending in the substrate; depositing a first dielectric layer over the substrate and the first and second conductive vias; receiving a waveguide; moving the waveguide to a location over the first dielectric layer and aligning the waveguide with a position of the first dielectric layer; attaching the waveguide to the position of the first dielectric layer; forming a first conductive member and a second conductive member over the waveguide, the first conductive member and the second conductive member being in contact with the waveguide; and etching a backside of the substrate to electrically expose the first and second conductive vias. The first conductive member or the second conductive member is electrically connected to the first or second conductive via.

    METHOD FOR FORMING SEMICONDUCTOR DEVICE
    3.
    发明申请
    METHOD FOR FORMING SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200273820A1

    公开(公告)日：2020-08-27

    申请号：US15930972

    申请日：2020-05-13

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： WEN-SHIANG LIAO ,  HUAN-NENG CHEN

    IPC分类号： H01L23/66 ,  H01L25/18 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L23/367

    摘要： A semiconductor device is disclosed. The semiconductor device includes a first die on a first substrate, a second die on a second substrate separate from the first substrate, a transmission line in a redistribution layer on a wafer, and a magnetic structure surrounds the transmission line. The first transmission line electrically connects the first die and the second die. The magnetic structure is configured to increase the characteristic impedance of the transmission line, which can save the current and power consumption of a current mirror and amplifier in a 3D IC chip-on-wafer-on-substrate (CoWoS) semiconductor package.

    WAVEGUIDE STRUCTURE AND METHOD FOR FORMING THE SAME
    5.
    发明申请
    WAVEGUIDE STRUCTURE AND METHOD FOR FORMING THE SAME 有权

    公开(公告)号：US20220019097A1

    公开(公告)日：2022-01-20

    申请号：US16933865

    申请日：2020-07-20

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： HUAN-NENG CHEN ,  FENG-WEI KUO ,  MIN-HSIANG HSU ,  LAN-CHOU CHO ,  CHEWN-PU JOU ,  WEN-SHIANG LIAO

    IPC分类号： G02F1/025

    摘要： An optical attenuating structure is provided. The optical attenuating structure includes a substrate, a waveguide, doping regions, an optical attenuating member, and a dielectric layer. The waveguide is extended over the substrate. The doping regions are disposed over the substrate, and include a first doping region, a second doping region opposite to the first doping region and separated from the first doping region by the waveguide, a first electrode extended over the substrate and in the first doping region, and a second electrode extended over the substrate and in the second doping region. The first optical attenuating member is coupled with the waveguide and disposed between the waveguide and the first electrode. The dielectric layer is disposed over the substrate and covers the waveguide, the doping regions and the first optical attenuating member.

    SEMICONDUCTOR PACKAGE DEVICE WITH INTEGRATED INDUCTOR AND MANUFACTURING METHOD THEREOF
    9.
    发明申请
    SEMICONDUCTOR PACKAGE DEVICE WITH INTEGRATED INDUCTOR AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20220336382A1

    公开(公告)日：2022-10-20

    申请号：US17808997

    申请日：2022-06-26

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： WEN-SHIANG LIAO ,  HUAN-NENG CHEN

    IPC分类号： H01L23/64 ,  H01L25/065 ,  H01L23/498 ,  H01L21/48 ,  H01L25/00

    摘要： A method includes: forming an interconnect structure over a semiconductor substrate. The interconnect structure includes: a magnetic core and a conductive coil winding around the magnetic core and electrically insulated from the magnetic core, wherein the conductive coil has horizontally-extending conductive lines and vertically-extending conductive vias electrically connecting the horizontally-extending conductive lines, wherein the magnetic core and the conductive coil are arranged in an inductor zone of the interconnect structure. The interconnect structure also includes a dielectric material electrically insulating the magnetic core from the conductive coil, and a connecting metal line adjacent to and on the outside of the inductor zone. The connecting metal line is electrical isolated from the inductor zone. The connecting metal line includes an upper surface lower than an upper surface of the second conductive vias and a bottom surface higher than a bottom surface of the first conductive vias.