公开(公告)号：US09646663B2

公开(公告)日：2017-05-09

申请号：US14751820

申请日：2015-06-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Ming-En Bu ,  Xiuli Yang ,  He-Zhou Wan ,  Mu-Jen Huang ,  Jie Cai

IPC分类号： G11C8/18 ,  G11C8/16 ,  G11C7/10 ,  G11C8/12

CPC分类号： G11C8/16 ,  G11C7/1075 ,  G11C8/12 ,  G11C8/18

摘要： In some embodiments, a circuit comprises a plurality of memory banks, a column line tracking loop and/or a row line tracking loop, and a tracking circuit. The plurality of memory banks are arranged in a plurality of rows and a plurality of columns of memory building blocks. The column line tracking loop traverses at least a portion of the plurality of rows. The row line tracking loop traverses at least a portion of the plurality of columns. The tracking circuit is configured to receive a first edge of a first signal, cause the first edge of a first signal to be propagated through the column line tracking loop and/or through the row line tracking loop and cause a second edge of the first signal when receiving the propagated first edge of the first signal. The first signal is associated with accessing of the plurality of memory banks.