公开(公告)号：US20240371926A1

公开(公告)日：2024-11-07

申请号：US18312819

申请日：2023-05-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： LIANG-YU SU ,  FU-YU CHU ,  MING-TA LEI ,  RUEY-HSIN LIU ,  YU-CHANG JONG ,  NAN-YING YANG ,  PO-YU CHIANG ,  YU-TING WEI

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/735

Abstract: A method includes: receiving the semiconductor device, wherein the semiconductor device includes: a well region; a doped region; a plurality of gate electrodes; a plurality of source regions; and a plurality of drain regions, wherein the plurality of gate electrodes, the plurality of source region and the plurality of drain regions form a plurality of transistors; and a bulk region disposed in the doped region. A first distance measured between a first transistor of the plurality of transistors and the bulk region is greater than a second distance measured between a second transistor of the plurality of transistors and the bulk region. The method further includes: applying a first voltage to the plurality of drain regions, wherein a first avalanche current generated around the first transistor and shunted through the bulk region is greater than a second avalanche current generated around the second transistor and shunted through the bulk region.

公开(公告)号：US20230387211A1

公开(公告)日：2023-11-30

申请号：US17827824

申请日：2022-05-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： YU-YING LAI ,  PO-CHIH SU ,  YU-TING WEI ,  RUEY-HSIN LIU

IPC: H01L29/10 ,  H01L27/088 ,  H01L21/74 ,  H01L21/8234

CPC classification number: H01L29/1083 ,  H01L27/088 ,  H01L21/74 ,  H01L21/823493 ,  H01L21/823481

Abstract: A high-voltage device includes a substrate, a gate structure over the substrate, a drain region disposed on a first side of the gate structure, a plurality of source regions disposed on a second side of the gate structure, and a plurality of doped regions disposed on the second side of the gate structure. The gate structure includes a plurality of first portions and a plurality of second portions alternately arranged. Width of the first portions are greater than widths of the second portions. The source regions are adjacent to the first portions of the gate structures, and the doped regions are adjacent to the second portions of the gate structure. The drain region and the source regions include dopants of a first conductivity type, and the doped regions include dopants of a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.