公开(公告)号：US12074603B1

公开(公告)日：2024-08-27

申请号：US18313384

申请日：2023-05-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Yu-Jheng Ou-Yang ,  Chi-Lin Liu ,  Shang-Chih Hsieh ,  Wei-Hsiang Ma ,  Kai-Chi Huang

IPC分类号： H03K3/037 ,  H03K3/3562

CPC分类号： H03K3/0372 ,  H03K3/0375 ,  H03K3/35625

摘要： The present disclosure provides a semiconductor device which includes a multiplexer, a master latch, and a slave latch. The multiplexer outputs an inverse of an input data signal or an inverse scan input signal according to a scan enable signal. The master latch is coupled to an output terminal of the multiplexer, and is configured to latch the inverse of the input data signal based on an input clock signal in response to the scan enable signal being in a low-logic state. The slave latch is coupled to the output terminal of the multiplexer through a first clocked CMOS inverter, and is configured to receive the input data signal and to output a latched slave latch data based on the input clock signal. A leakage-free dummy cell is disposed in a non-critical path of the master latch and the slave latch.