公开(公告)号：US20120044766A1

公开(公告)日：2012-02-23

申请号：US13285099

申请日：2011-10-31

申请人： TAKESHI NAKANO ,  Hiroshi Nakamura ,  Koji Hosono

发明人： TAKESHI NAKANO ,  Hiroshi Nakamura ,  Koji Hosono

IPC分类号： G11C16/04

CPC分类号： G11C16/08

摘要： A semiconductor memory device includes a transfer circuit and a control circuit. The transfer circuit which includes a p-type MOS transistor with a source to which is applied a first voltage and an n-type MOS transistor to whose gate the drain of the p-type MOS transistor is connected and the first voltage is transferred, to whose source a second voltage is applied, and whose drain is connected to a load. The control circuit which turns the p-type MOS transistor on and off and which turns the p-type MOS transistor on to make the p-type MOS transistor transfer the second voltage to the load and, during the transfer, turns the p-type MOS transistor off to make the gate of the n-type MOS transistor float at the first voltage.

摘要翻译： 半导体存储器件包括转移电路和控制电路。 该传输电路包括一个p型MOS晶体管，其源极被施加第一电压，一个n型MOS晶体管被连接到p型MOS晶体管的漏极并且第一个电压被传输到其栅极，到 其源极施加第二电压，并且其漏极连接到负载。 控制电路使p型MOS晶体管导通和关断，并使p型MOS晶体管导通，使p型MOS晶体管将第二电压转移到负载，并且在传输期间使p型MOS晶体管转换为p型 MOS晶体管关闭，使n型MOS晶体管的栅极浮在第一电压。