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    Semiconductor memory device with a stacked gate including a charge storage layer and a control gate and method of controlling the same
    1.
    发明授权
    Semiconductor memory device with a stacked gate including a charge storage layer and a control gate and method of controlling the same 有权
    具有包括电荷存储层和控制栅极的堆叠栅极的半导体存储器件及其控制方法

    公开(公告)号：US08077523B2

    公开(公告)日：2011-12-13

    申请号：US12406382

    申请日：2009-03-18

    申请人： Takeshi Nakano ,  Hiroshi Nakamura ,  Koji Hosono

    发明人： Takeshi Nakano ,  Hiroshi Nakamura ,  Koji Hosono

    IPC分类号： G11C11/34 ,  G11C16/06

    CPC分类号： G11C16/08

    摘要： A semiconductor memory device includes a transfer circuit and a control circuit. The transfer circuit which includes a p-type MOS transistor with a source to which is applied a first voltage and an n-type MOS transistor to whose gate the drain of the p-type MOS transistor is connected and the first voltage is transferred, to whose source a second voltage is applied, and whose drain is connected to a load. The control circuit which turns the p-type MOS transistor on and off and which turns the p-type MOS transistor on to make the p-type MOS transistor transfer the second voltage to the load and, during the transfer, turns the p-type MOS transistor off to make the gate of the n-type MOS transistor float at the first voltage.

    摘要翻译： 半导体存储器件包括转移电路和控制电路。 该传输电路包括一个p型MOS晶体管，其源极被施加第一电压，一个n型MOS晶体管被连接到p型MOS晶体管的漏极并且第一个电压被传输到其栅极，到 其源极施加第二电压，并且其漏极连接到负载。 控制电路使p型MOS晶体管导通和关断，并使p型MOS晶体管导通，使p型MOS晶体管将第二电压转移到负载，并且在传输期间使p型MOS晶体管转换为p型 MOS晶体管关闭，使n型MOS晶体管的栅极浮在第一电压。

    Semiconductor memory device with a stacked gate including a charge storage layer and a control gate and method of controlling the same
    2.
    发明授权
    Semiconductor memory device with a stacked gate including a charge storage layer and a control gate and method of controlling the same 有权
    具有包括电荷存储层和控制栅极的堆叠栅极的半导体存储器件及其控制方法

    公开(公告)号：US08335125B2

    公开(公告)日：2012-12-18

    申请号：US13285099

    申请日：2011-10-31

    申请人： Takeshi Nakano ,  Hiroshi Nakamura ,  Koji Hosono

    发明人： Takeshi Nakano ,  Hiroshi Nakamura ,  Koji Hosono

    IPC分类号： G11C8/00

    CPC分类号： G11C16/08

    摘要： A semiconductor memory device includes a transfer circuit and a control circuit. The transfer circuit which includes a p-type MOS transistor with a source to which is applied a first voltage and an n-type MOS transistor to whose gate the drain of the p-type MOS transistor is connected and the first voltage is transferred, to whose source a second voltage is applied, and whose drain is connected to a load. The control circuit which turns the p-type MOS transistor on and off and which turns the p-type MOS transistor on to make the p-type MOS transistor transfer the second voltage to the load and, during the transfer, turns the p-type MOS transistor off to make the gate of the n-type MOS transistor float at the first voltage.

    摘要翻译： 半导体存储器件包括转移电路和控制电路。 该传输电路包括一个p型MOS晶体管，其源极被施加第一电压，一个n型MOS晶体管被连接到p型MOS晶体管的漏极并且第一个电压被传输到其栅极，到 其源极施加第二电压，并且其漏极连接到负载。 控制电路使p型MOS晶体管导通和关断，并使p型MOS晶体管导通，使p型MOS晶体管将第二电压转移到负载，并且在传输期间使p型MOS晶体管转换为p型 MOS晶体管关闭，使n型MOS晶体管的栅极浮在第一电压。

    SEMICONDUCTOR MEMORY DEVICE WITH A STACKED GATE INCLUDING A CHARGE STORAGE LAYER AND A CONTROL GATE AND METHOD OF CONTROLLING THE SAME
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE WITH A STACKED GATE INCLUDING A CHARGE STORAGE LAYER AND A CONTROL GATE AND METHOD OF CONTROLLING THE SAME 有权
    具有包括充电储存层的堆叠门和控制门的半导体存储器件及其控制方法

    公开(公告)号：US20120044766A1

    公开(公告)日：2012-02-23

    申请号：US13285099

    申请日：2011-10-31

    申请人： TAKESHI NAKANO ,  Hiroshi Nakamura ,  Koji Hosono

    发明人： TAKESHI NAKANO ,  Hiroshi Nakamura ,  Koji Hosono

    IPC分类号： G11C16/04

    CPC分类号： G11C16/08

    摘要： A semiconductor memory device includes a transfer circuit and a control circuit. The transfer circuit which includes a p-type MOS transistor with a source to which is applied a first voltage and an n-type MOS transistor to whose gate the drain of the p-type MOS transistor is connected and the first voltage is transferred, to whose source a second voltage is applied, and whose drain is connected to a load. The control circuit which turns the p-type MOS transistor on and off and which turns the p-type MOS transistor on to make the p-type MOS transistor transfer the second voltage to the load and, during the transfer, turns the p-type MOS transistor off to make the gate of the n-type MOS transistor float at the first voltage.

    摘要翻译： 半导体存储器件包括转移电路和控制电路。 该传输电路包括一个p型MOS晶体管，其源极被施加第一电压，一个n型MOS晶体管被连接到p型MOS晶体管的漏极并且第一个电压被传输到其栅极，到 其源极施加第二电压，并且其漏极连接到负载。 控制电路使p型MOS晶体管导通和关断，并使p型MOS晶体管导通，使p型MOS晶体管将第二电压转移到负载，并且在传输期间使p型MOS晶体管转换为p型 MOS晶体管关闭，使n型MOS晶体管的栅极浮在第一电压。

    Non-volatile semiconductor memory device
    5.
    发明授权
    Non-volatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US07586785B2

    公开(公告)日：2009-09-08

    申请号：US12020981

    申请日：2008-01-28

    申请人： Koji Hosono ,  Kenichi Imamiya ,  Hiroshi Nakamura

    发明人： Koji Hosono ,  Kenichi Imamiya ,  Hiroshi Nakamura

    IPC分类号： G11C16/04

    CPC分类号： G11C16/105 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/102 ,  G11C16/26 ,  G11C2216/14

    摘要： A non-volatile semiconductor memory device includes a memory cell array with electrically rewritable non-volatile memory cells laid out therein, an address selector circuit for performing memory cell selection of the memory cell array, a data read/write circuit arranged to perform data read of the memory cell array and data write to the memory cell array, and a control circuit for executing a series of copy write operations in such a manner that a data output operation of from the data read/write circuit to outside of a chip and a data write operation of from the data read/write circuit to the memory cell array are overlapped each other, the copy write operation including reading data at a certain address of the memory cell array into the data read/write circuit, outputting read data held in the read/write circuit to outside of the chip and writing write data into another address of the memory cell array, the write data being a modified version of the read data held in the data read/write circuit as externally created outside the chip.

    摘要翻译： 一种非易失性半导体存储器件包括其中布置有电可重写非易失性存储器单元的存储单元阵列，用于执行存储单元阵列的存储单元选择的地址选择器电路，布置成执行数据读取的数据读/写电路 的存储单元阵列和写入存储单元阵列的数据;以及控制电路，用于执行一系列复制写入操作，使得从数据读/写电路到芯片外部的数据输出操作和 从数据读/写电路到存储单元阵列的数据写入操作彼此重叠，复制写操作包括将存储单元阵列的特定地址处的数据读入数据读/写电路，输出保持在 读/写电路到芯片外部，并将写入数据写入存储单元阵列的另一个地址，写数据是保存在数据读/写中的读数据的修改版本 ite电路在芯片外部外部创建。

    Sense amplifier circuit in multi-level non-volatile semiconductor memory comprising a boosting capacitor for boosting the potential at sense node
    6.
    发明授权
    Sense amplifier circuit in multi-level non-volatile semiconductor memory comprising a boosting capacitor for boosting the potential at sense node 有权
    多级非易失性半导体存储器中的感测放大器电路，包括用于在感测节点处升高电位的升压电容器

    公开(公告)号：US07567463B2

    公开(公告)日：2009-07-28

    申请号：US12123157

    申请日：2008-05-19

    申请人： Koji Hosono ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Kenichi Imamiya

    发明人： Koji Hosono ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Kenichi Imamiya

    IPC分类号： G11C11/34 ,  G11C16/06

    CPC分类号： G11C16/0483 ,  G11C5/145 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643

    摘要： A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.

    摘要翻译： 非易失性半导体器件具有存储单元阵列，其具有电可擦除可编程非易失性存储器单元，重新编程和检索电路，其临时存储要存储在存储单元阵列中的要编程的数据并感测从存储器单元阵列检索的数据。 每个重新编程和检索电路具有选择性地连接到存储单元阵列和传送数据的第一和第二锁存器。 控制器控制数据重新编程操作中的重新编程和检索电路以及来自存储单元阵列的数据检索操作。 每个重新编程和检索电路都具有多级逻辑操作模式和缓存操作模式。 在多级逻辑操作模式中，使用第一和第二锁存器来执行二位四电平数据的高位和低位的重新编程和检索，以将两位四电平数据存储在存储单元之一中 在预定的阈值电平范围内。 在高速缓存操作模式中，根据第一地址选择的存储器单元之一和第一锁存器之间的数据传输是在第二锁存器和输入/输出端子之间根据第二地址相对于 要存储在其中一个存储单元中的一位二电平数据。

    Method of transferring initially-setting data in a non-volatile semiconductor memory
    8.
    发明授权
    Method of transferring initially-setting data in a non-volatile semiconductor memory 有权
    在非易失性半导体存储器中传送初始设置数据的方法

    公开(公告)号：US07126851B2

    公开(公告)日：2006-10-24

    申请号：US10989372

    申请日：2004-11-17

    申请人： Koji Hosono ,  Toshihiko Himeno ,  Kenichi Imamiya ,  Hiroshi Nakamura

    发明人： Koji Hosono ,  Toshihiko Himeno ,  Kenichi Imamiya ,  Hiroshi Nakamura

    IPC分类号： G11C16/06

    CPC分类号： G11C29/789 ,  G11C7/20 ,  G11C16/20 ,  G11C2029/4402

    摘要： A non-volatile semiconductor memory includes a memory cell array having a plurality of electrically-rewritable non-volatile memory cells. The memory cell array is provided with an initially-setting data area, programmed in which is initially-setting data for deciding memory operation requirements. The non-volatile semiconductor memory also includes an initial-set data latch. The initially-setting data of the memory cell array is read out and transferred to the data latch in an initially-setting operation.

    摘要翻译： 非易失性半导体存储器包括具有多个电可重写非易失性存储单元的存储单元阵列。 存储单元阵列设置有初始设置的数据区，其中编程有初始设置数据，用于决定存储器操作要求。 非易失性半导体存储器还包括初始设置数据锁存器。 在初始设置操作中，存储单元阵列的初始设置数据被读出并传送到数据锁存器。