公开(公告)号：US12144183B2

公开(公告)日：2024-11-12

申请号：US17271875

申请日：2020-02-27

Applicant: TDK CORPORATION

Inventor： Yukio Terasaki

IPC: H10B61/00 ,  G06N3/049 ,  G06N3/063 ,  H10N50/10 ,  H10N59/00

Abstract: An arithmetic operation circuit including: a variable resistance element that includes three terminals that are a first terminal, a second terminal, and a third terminal and is configured to be able to change a resistance value; a first electrode connected to the first terminal; a second electrode; a third electrode; a first switching element connected between the second electrode and the second terminal; a second switching element connected between the third electrode and the third terminal; and a capacitor connected between a transmission line connecting the second terminal and the first switching element and the ground.

公开(公告)号：US11551071B2

公开(公告)日：2023-01-10

申请号：US16826691

申请日：2020-03-23

Applicant: TDK CORPORATION

Inventor： Yukio Terasaki

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08

Abstract: A neural network device includes a decimation unit configured to convert a discrete value of an input signal to a discrete value having a smaller step number than a quantization step number of the input signal on the basis of a predetermined threshold value to generate a decimation signal a modulation unit configured to modulate a discrete value of the decimation signal generated by the decimation unit to generate a modulation signal indicating the discrete value of the decimation signal, and a weighting unit including a neuromorphic element configured to output a weighted signal obtained by weighting the modulation signal through multiplication of the modulation signal generated by the modulation unit by a weight according to a value of a variable characteristic.

公开(公告)号：US11335849B2

公开(公告)日：2022-05-17

申请号：US16191893

申请日：2018-11-15

Applicant: TDK CORPORATION

Inventor： Shogo Yamada ,  Tomoyuki Sasaki ,  Yukio Terasaki ,  Tatsuo Shibata

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/10

Abstract: A magnetic domain wall displacement type magnetic recording element which comprises: a first magnetization fixed part which is stacked in a first direction, a magnetic recording layer which includes a magnetic domain wall and extends in a second direction which crosses with the first direction, a non-magnetic layer which is provided between the first magnetization fixed part and the magnetic recording layer, and a first via part which is electrically connected to the magnetic recording layer, wherein at least a part of the first via part is located at a position which is apart from the first magnetization fixed part in the second direction in planar view observed from the first direction, the magnetic recording layer includes a first part which has a position where the first magnetization fixed part overlaps with the magnetic recording layer in planar view observed from the first direction, and a width of the first via part in a third direction which is orthogonal to the second direction is larger than a width of said position of the first part of the magnetic recording layer.

公开(公告)号：US11635941B2

公开(公告)日：2023-04-25

申请号：US16643660

申请日：2018-02-19

Applicant: TDK CORPORATION

Inventor： Yukio Terasaki

IPC: G06F7/544 ,  G06F7/523

Abstract: A controller is a controller of an array including a neuromorphic element that multiplies a weight based on a value of a variable characteristic by a signal, and includes a control unit that controls the characteristic of the neuromorphic element by using a discretization step size obtained so that a predetermined condition for reducing an error or a predetermined condition for improving accuracy is satisfied on the basis of a case where a true value of the weight obtained with a higher accuracy than a resolution of the characteristic of the neuromorphic element is used and a case where a discretization step size which is set for the characteristic of the neuromorphic element is used.

公开(公告)号：US11340869B2

公开(公告)日：2022-05-24

申请号：US16675423

申请日：2019-11-06

Applicant: TDK CORPORATION

Inventor： Yukio Terasaki

IPC: G06F7/544 ,  G06N3/063

Abstract: A sum-of-products operator including: a first circuit configured to generate a plurality of signals, each of which corresponds to each of a plurality of data; a second circuit including a first operation circuit configured to multiply each of the signals generated by the first circuit by a weight using a plurality of variable resistive elements having variable resistance values, and to calculate a sum of a plurality of results of multiplications; a third circuit configured to calculate a result of summing values corresponding to the data or a result of the summing value after being adjusted; and a fourth circuit including a differential circuit configured to output a difference between a calculated result in the first operation circuit of the second circuit and a calculated result in the third circuit.