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公开(公告)号：US20200235571A1
公开(公告)日：2020-07-23
申请号：US16558867
申请日：2019-09-03
Applicant: Texas Instruments Incorporated
Inventor： Ann Margaret Concannon , Vishwanath Joshi , Antonio Gallerano , Zhao Gao , Yanqing Li
Abstract: A protection circuit for a signal processor, a method of operating the protection circuit, and a method of forming the protection circuit. In one example, the protection circuit is couplable to a signal port and a first power bus for the signal processor. The protection circuit includes a first diode string couplable across the signal port and the first power bus. The first diode string includes a first diode and a second diode coupled in series in a same polarity sense. The protection circuit also includes a third diode coupled in parallel with one of the first diode and the second diode in an opposite polarity sense.
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公开(公告)号：US10163888B2
公开(公告)日：2018-12-25
申请号：US15359833
申请日：2016-11-23
Applicant: Texas Instruments Incorporated
IPC: H01L27/02 , H01L29/747 , H01L29/06 , H01L29/74
Abstract: Disclosed examples provide an ESD protection circuit including a protection structure to selectively conduct current between a first terminal at a protected node and a second terminal at a reference node in response to the protected node voltage and a control voltage signal rising above a trigger voltage during an ESD event, and a bias circuit configured to bias a protection structure control terminal at a control voltage corresponding to a higher one of a first voltage of the first terminal and a second voltage of the second terminal to control the trigger voltage of the ESD protection structure to keep the ESD protection structure off during normal operation.
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公开(公告)号：US20190109127A1
公开(公告)日：2019-04-11
申请号：US16199265
申请日：2018-11-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
IPC: H01L27/02 , H01L29/06 , H01L29/747 , H01L29/74
Abstract: Disclosed examples provide an ESD protection circuit including a protection structure to selectively conduct current between a first terminal at a protected node and a second terminal at a reference node in response to the protected node voltage and a control voltage signal rising above a trigger voltage during an ESD event, and a bias circuit configured to bias a protection structure control terminal at a control voltage corresponding to a higher one of a first voltage of the first terminal and a second voltage of the second terminal to control the trigger voltage of the ESD protection structure to keep the ESD protection structure off during normal operation.
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公开(公告)号：US11271392B2
公开(公告)日：2022-03-08
申请号：US16558867
申请日：2019-09-03
Applicant: Texas Instruments Incorporated
Inventor： Ann Margaret Concannon , Vishwanath Joshi , Antonio Gallerano , Zhao Gao , Yanqing Li
Abstract: A protection circuit for a signal processor, a method of operating the protection circuit, and a method of forming the protection circuit. In one example, the protection circuit is couplable to a signal port and a first power bus for the signal processor. The protection circuit includes a first diode string couplable across the signal port and the first power bus. The first diode string includes a first diode and a second diode coupled in series in a same polarity sense. The protection circuit also includes a third diode coupled in parallel with one of the first diode and the second diode in an opposite polarity sense.
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Patent Agency Ranking
公开(公告)号：US11239229B2
公开(公告)日：2022-02-01
申请号：US16199265
申请日：2018-11-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
IPC: H01L27/02 , H01L29/06 , H01L29/74 , H01L29/747
Abstract: Disclosed examples provide an ESD protection circuit including a protection structure to selectively conduct current between a first terminal at a protected node and a second terminal at a reference node in response to the protected node voltage and a control voltage signal rising above a trigger voltage during an ESD event, and a bias circuit configured to bias a protection structure control terminal at a control voltage corresponding to a higher one of a first voltage of the first terminal and a second voltage of the second terminal to control the trigger voltage of the ESD protection structure to keep the ESD protection structure off during normal operation.
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公开(公告)号：US10439024B2
公开(公告)日：2019-10-08
申请号：US15180592
申请日：2016-06-13
Inventor： Karim-Thomas Taghizadeh Kaschani , Antonio Gallerano
Abstract: A semiconductor device includes a substrate having a semiconductor surface doped a second dopant type with a buried layer (BL) doped a first dopant type. First, second and third well regions doped the second dopant type are on top of the BL. Second doped regions doped the first dopant type on top of and contacting the BL arraigned as a first well ring and second well ring are around the first and third well regions respectively. At least one high-injection component including the first well region is surrounded by the first well ring. At least one component including the third well region is surrounded by the second well ring. An npn or pnp guard wall pocket including a wall of the first and second well rings, and the second well region is between the high-injection component and the component.
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公开(公告)号：US11121210B2
公开(公告)日：2021-09-14
申请号：US16560062
申请日：2019-09-04
Applicant: Texas Instruments Incorporated
Inventor： Karim-Thomas Taghizadeh Kaschani , Antonio Gallerano
Abstract: A semiconductor device includes a substrate having a semiconductor surface doped a second dopant type with a buried layer (BL) doped a first dopant type. First, second and third well regions doped the second dopant type are on top of the BL. Second doped regions doped the first dopant type on top of and contacting the BL arraigned as a first well ring and second well ring are around the first and third well regions respectively. At least one high-injection component including the first well region is surrounded by the first well ring. At least one component including the third well region is surrounded by the second well ring. An npn or pnp guard wall pocket including a wall of the first and second well rings, and the second well region is between the high-injection component and the component.
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公开(公告)号：US10454269B2
公开(公告)日：2019-10-22
申请号：US15581173
申请日：2017-04-28
Applicant: Texas Instruments Incorporated
Inventor： Xianzhi Dai , Antonio Gallerano
Abstract: An electrostatic discharge (ESD) protection circuit includes an active shunt transistor, a first pull-down transistor, and a second pull-down transistor. The active shunt transistor is coupled between a first I/O pad and a reference voltage. The first pull-down transistor is connected to the reference voltage. The second pull-down transistor is connected to the first pull-down transistor and the first I/O pad. The first pull-down transistor and the second pull-down transistor are in separate isolation tanks of an isolation deep n-well.
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公开(公告)号：US20180145064A1
公开(公告)日：2018-05-24
申请号：US15359833
申请日：2016-11-23
Applicant: Texas Instruments Incorporated
IPC: H01L27/02 , H01L29/747 , H01L29/74 , H01L29/06
CPC classification number: H01L27/0248 , H01L29/0649 , H01L29/7436 , H01L29/747
Abstract: Disclosed examples provide an ESD protection circuit including a protection structure to selectively conduct current between a first terminal at a protected node and a second terminal at a reference node in response to the protected node voltage and a control voltage signal rising above a trigger voltage during an ESD event, and a bias circuit configured to bias a protection structure control terminal at a control voltage corresponding to a higher one of a first voltage of the first terminal and a second voltage of the second terminal to control the trigger voltage of the ESD protection structure to keep the ESD protection structure off during normal operation.
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