公开(公告)号：US20230120432A1

公开(公告)日：2023-04-20

申请号：US17956351

申请日：2022-09-29

Applicant: Texas Instruments Incorporated

Inventor： Austin Womac ,  Ryan Lind ,  Richard Stair

IPC: H02M3/158 ,  H02M1/32 ,  G05F1/59 ,  H03K19/20 ,  H03K17/687 ,  H03K17/081 ,  H02J7/00

Abstract: In a voltage converter, a blocking transistor has a conduction path between a power terminal and a converter terminal. A body diode of the blocking transistor: conducts current from the power terminal to the converter terminal; and blocks current from the converter terminal to the power terminal. A first switching transistor has a conduction path between the converter terminal and a switching terminal. A second switching transistor has a conduction path between the switching terminal and a ground terminal. A first gate driver has an output coupled to a control terminal of the first switching transistor. A second gate driver has an output coupled to a control terminal of the second switching transistor. A driver circuit has an output coupled to a control terminal of the blocking transistor. A bootstrap terminal of the driver circuit is coupled to a bias input of the first gate driver.

公开(公告)号：US11159032B2

公开(公告)日：2021-10-26

申请号：US16528248

申请日：2019-07-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Austin Womac ,  Eric Southard ,  Orlando Lazaro

IPC: H01M10/46 ,  H02J7/00 ,  H02M7/48

Abstract: Aspects of the disclosure include a first sense transistor having a gate and a drain configured to couple in parallel with a high-side transistor and a source terminal coupled to a first node, and a second sense transistor having a gate and a drain configured to couple in parallel with a low-side transistor, and a source terminal coupled to a third node. The circuit further includes a first comparator circuit having a first input coupled to the first node, a second input coupled to a second node, and an output, a second comparator circuit having a first input coupled to the third node, a second input coupled to a ground node, and an output, and a logic circuit having first input coupled to the output of the first comparator circuit, a second input coupled to the output of the second comparator circuit, and an output.