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公开(公告)号：US20250141352A1
公开(公告)日：2025-05-01
申请号：US18498163
申请日：2023-10-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Bradford Hunter , Jing Ye , Xiaogiu Summer Huang , Terry Sculley
Abstract: An integrated circuit comprises a charge pump connected to a power source terminal and to a ground terminal, the charge pump having a charge pump output terminal; and a switch matrix having a plurality of switch matrix inputs and a plurality of switch matrix outputs, wherein pairs of the plurality of switch matrix outputs are connected to respective ones of a respective plurality of output terminals, and wherein the charge pump output terminal is connected to a first subset comprising at least three of the plurality of switch matrix inputs.
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公开(公告)号：US20250123642A1
公开(公告)日：2025-04-17
申请号：US18989855
申请日：2024-12-20
Applicant: Texas Instruments Incorporated
Inventor： Bradford Hunter
Abstract: An example cascode voltage regulator circuit includes a first transistor coupled to an input voltage terminal and configured as a source follower to provide an output voltage at a source terminal, a second transistor coupled in series between the source terminal of the first transistor and an output terminal, the second transistor configured as a current limiter, and a current mirror coupled between respective first and second control terminals of the first and second transistors, the current mirror configured to receive a first current indicative of a source follower current flowing through the first transistor and to turn off the second transistor by coupling the first and second control terminals together responsive to the source follower current exceeding a threshold. In an example, the first transistor is a drain-extended NMOS device and the second transistor is a drain-extended PMOS device.
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Patent Agency Ranking
公开(公告)号：US20240283258A1
公开(公告)日：2024-08-22
申请号：US18239997
申请日：2023-08-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Yang Wu , Yihua Yang , Xiaodong Cai , Bradford Hunter
IPC: H02J7/00
CPC classification number: H02J7/0019 , H02J7/0047
Abstract: Described examples include a system having a power source having a first output terminal and a second output terminal and a controller. The system also has a selective charger coupled to the controller, the selective charger configured to couple, in response to instructions from the controller, the first output terminal of the power source to a first node that is configured to be coupled to a first terminal of a selected battery cell of two or more serially coupled battery cells, and couple the second output terminal of the power source to a second node configured to be coupled to a second battery terminal of the selected battery cell.
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公开(公告)号：US20230402918A1
公开(公告)日：2023-12-14
申请号：US17829246
申请日：2022-05-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Bradford Hunter
IPC: H02M3/156 , H02M3/07 , H03M1/18 , H03K19/173
CPC classification number: H02M3/1563 , H03K19/1737 , H03M1/185 , H02M3/078
Abstract: A circuit includes a switched capacitor circuit and a voltage generator circuit. The switched capacitor circuit includes first, second, third, and fourth switches and first and second capacitors. The first capacitor has first and second terminals, the first terminal coupled to the first switch. The second capacitor has first and second terminals, the second terminal coupled to the second switch. The third switch has a terminal coupled to the second terminals of the first and second capacitors. The fourth switch has first and second terminals, the first terminal coupled the terminal of the third switch and to the second terminals of the first and second capacitors. The voltage generator circuit has an output coupled to the second terminal of the fourth switch and is configured to provide a common mode output bias voltage at the second terminal of the fourth switch responsive to a common mode input bias voltage.
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公开(公告)号：US12204354B2
公开(公告)日：2025-01-21
申请号：US18305960
申请日：2023-04-24
Applicant: Texas Instruments Incorporated
Inventor： Bradford Hunter
Abstract: An example cascode voltage regulator circuit includes a first transistor coupled to an input voltage terminal and configured as a source follower to provide an output voltage at a source terminal, a second transistor coupled in series between the source terminal of the first transistor and an output terminal, the second transistor configured as a current limiter, and a current mirror coupled between respective first and second control terminals of the first and second transistors, the current mirror configured to receive a first current indicative of a source follower current flowing through the first transistor and to turn off the second transistor by coupling the first and second control terminals together responsive to the source follower current exceeding a threshold. In an example, the first transistor is a drain-extended NMOS device and the second transistor is a drain-extended PMOS device.
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公开(公告)号：US12155300B2
公开(公告)日：2024-11-26
申请号：US17829246
申请日：2022-05-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Bradford Hunter
IPC: H02M3/07 , H03K19/173
Abstract: A circuit includes a switched capacitor circuit and a voltage generator circuit. The switched capacitor circuit includes first, second, third, and fourth switches and first and second capacitors. The first capacitor has first and second terminals, the first terminal coupled to the first switch. The second capacitor has first and second terminals, the second terminal coupled to the second switch. The third switch has a terminal coupled to the second terminals of the first and second capacitors. The fourth switch has first and second terminals, the first terminal coupled the terminal of the third switch and to the second terminals of the first and second capacitors. The voltage generator circuit has an output coupled to the second terminal of the fourth switch and is configured to provide a common mode output bias voltage at the second terminal of the fourth switch responsive to a common mode input bias voltage.
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公开(公告)号：US20240353880A1
公开(公告)日：2024-10-24
申请号：US18305960
申请日：2023-04-24
Applicant: Texas Instruments Incorporated
Inventor： Bradford Hunter
Abstract: An example cascode voltage regulator circuit includes a first transistor coupled to an input voltage terminal and configured as a source follower to provide an output voltage at a source terminal, a second transistor coupled in series between the source terminal of the first transistor and an output terminal, the second transistor configured as a current limiter, and a current mirror coupled between respective first and second control terminals of the first and second transistors, the current mirror configured to receive a first current indicative of a source follower current flowing through the first transistor and to turn off the second transistor by coupling the first and second control terminals together responsive to the source follower current exceeding a threshold. In an example, the first transistor is a drain-extended NMOS device and the second transistor is a drain-extended PMOS device.
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