公开(公告)号：US11755342B2

公开(公告)日：2023-09-12

申请号：US17123407

申请日：2020-12-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ronald Nerlich ,  Mark Jung ,  Johann Zipperer ,  Dietmar Walther

IPC: G05B1/03 ,  G06F9/448 ,  G06F8/34 ,  G05B19/045

CPC classification number: G06F9/4498 ,  G05B19/045 ,  G06F8/34

Abstract: A circuit includes a guard trigger circuit that includes a first input node adapted to be coupled to a first state signal, a second input node adapted to be coupled to a second state signal and an output node. The circuit also includes a reset synchronizer circuit that includes an input node coupled to the output node of the guard trigger circuit, a clock node adapted to be coupled to a clock signal and an output node. The circuit further includes a timeout circuit including an input node coupled to the output node of the reset synchronizer circuit, a clock node adapted to be coupled to the clock signal and an output node. The circuit still further includes a reset requestor circuit that includes a first input node coupled to the output node of the guard trigger circuit, a second node coupled to the output node of the timeout circuit.

公开(公告)号：US12248793B2

公开(公告)日：2025-03-11

申请号：US18465213

申请日：2023-09-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ronald Nerlich ,  Mark Jung ,  Johann Zipperer ,  Dietmar Walther

IPC: G05B1/03 ,  G05B19/045 ,  G06F8/34 ,  G06F9/448

Abstract: A circuit includes a guard trigger circuit that includes a first input node adapted to be coupled to a first state signal, a second input node adapted to be coupled to a second state signal and an output node. The circuit also includes a reset synchronizer circuit that includes an input node coupled to the output node of the guard trigger circuit, a clock node adapted to be coupled to a clock signal and an output node. The circuit further includes a timeout circuit including an input node coupled to the output node of the reset synchronizer circuit, a clock node adapted to be coupled to the clock signal and an output node. The circuit still further includes a reset requestor circuit that includes a first input node coupled to the output node of the guard trigger circuit, a second node coupled to the output node of the timeout circuit.