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公开(公告)号：US20170207774A1
公开(公告)日：2017-07-20
申请号：US15408412
申请日：2017-01-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Diptendu Ghosh , Petteri Matti Litmanen , Siraj Akhtar
CPC classification number: H03K5/00006 , H03K3/356139
Abstract: A latch circuit includes first and second inverters, each with latching (inner) and clocking (outer) PMOS/NMOS transistor pairs in a series/stack configuration. A first inverter includes a D_latching PMOS/NMOS transistor pair, drain-connected at a D node. A first /clock PMOS transistor is coupled between a high rail and a source terminal of the D_latching PMOS transistor, and a first clock NMOS transistor is coupled between a low rail and the source terminal of the D_latching NMOS transistor. A second inverter includes a Dbar_latching PMOS/NMOS transistor pair, drain-connected at a Dbar node. A second /clock PMOS transistor is coupled between the high rail and the source terminal of the Dbar_latching PMOS transistor, and a second clock NMOS transistor is coupled between the low rail and the Dbar_latching NMOS transistor. A cross-coupling switch circuit connected between the D node and the Dbar node. The first and second /clock PMOS transistors can be combined as a single /clock PMOS transistor connected between the high rail and the source terminals of respectively the D_latching and Dbar_latching PMOS transistors, and the first and second clock NMOS transistors can be combined as a single clock NMOS transistor connected between the low rail and the source terminals of respectively the D_latching and Dbar_latching NMOS transistors. As an example application, the latch circuit can be used in a quadrature (IQ) frequency divider.
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公开(公告)号：US09900022B2
公开(公告)日：2018-02-20
申请号：US15408396
申请日：2017-01-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Diptendu Ghosh , Petteri Matti Litmanen , Siraj Akhtar
CPC classification number: H03H7/0115 , H03M1/0631 , H03M1/66
Abstract: DAC design uses a passive reconstruction filter. The reconstruction filter includes a notch filter and series peaking filter. The notch filter provides notch filtering at the DAC clock frequency. The peaking filter increases signal bandwidth while attenuating frequency content at harmonics of the DAC clock frequency. The notch filter can be an LC notch filter with a notch inductor Ln and a notch capacitor Cn. The peaking filter can be a series peaking inductor Ls (shunted with a filter capacitor Cp). In a differential configuration, the passive reconstruction filter can be ±LC notch filters (with ±Ln notch inductors), and the peaking filter can be ±Ls peaking inductors coupled in series to the ±LC notch filters. The ±Ln notch inductors, ±Ls peaking inductors can be mutually wound as single inductors. For an example direct conversion RF transmit chain, IQ± signal paths are implemented with differential DAC designs including passive reconstruction filters.
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公开(公告)号：US20170207795A1
公开(公告)日：2017-07-20
申请号：US15408396
申请日：2017-01-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Diptendu Ghosh , Petteri Matti Litmanen , Siraj Akhtar
CPC classification number: H03H7/0115 , H03M1/0631 , H03M1/66
Abstract: A DAC design uses a passive reconstruction filter. The reconstruction filter includes a notch filter and series peaking filter (low pass filter with peaking in the signal passband). The notch filter provides notch filtering at the DAC clock frequency. The peaking filter increases signal bandwidth while attenuating frequency contents at harmonics of the DAC clock frequency. The notch filter can be an LC notch filter with at least one notch inductor Ln and at least one notch capacitor Cn. The peaking filter can be a series peaking inductor Ls (shunted with a filter capacitor Cp). In a differential configuration, the passive reconstruction filter can be configured with ±LC notch filters (with ±Ln notch inductors), and the peaking filter can be ±Ls peaking inductors coupled in series to the ±LC notch filters. The ±Ln notch inductors, ±Ls peaking inductors can be mutually wound as single inductors. For an example direct conversion RF transmit chain, IQ± signal paths are implemented with differential DAC designs including passive reconstruction filters.
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