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公开(公告)号：US20230025757A1
公开(公告)日：2023-01-26
申请号：US17489483
申请日：2021-09-29
Applicant: Texas Instruments Incorporated
Inventor： RR Manikandan , Kumar Anurag Shrivastava , Robert Floyd Payne , Anant Shankar Kamath , Swaminathan Sankaran , Kishalay Datta , Siraj Akhtar , Mark Edward Wentroble , Suvadip Banerjee , Rakesh Hariharan , Gurumurti Kailaschandra Avhad
Abstract: In described examples, an integrated circuit includes an on-off keying (OOK) digital isolator, which includes a first circuitry, a multiplexer, an OOK modulator, an isolation barrier, an OOK envelope detector, and a second circuitry. The first circuitry generates and outputs a calibration signal. The multiplexer has a data signal input, and an input coupled to a first circuitry output. An OOK modulator input is coupled to a multiplexer output. An isolation barrier input is coupled to an OOK modulator output. An OOK envelope detector input is coupled to an isolation barrier output. The second circuitry includes an input coupled to an OOK envelope detector output, and an output coupled to an OOK envelope detector control input. The second circuitry detects a duty cycle distortion (DCD) of the OOK envelope detector output, and outputs a control signal to change the OOK envelope detector output's duty cycle based on the detected DCD.
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公开(公告)号：US11088696B2
公开(公告)日：2021-08-10
申请号：US16731739
申请日：2019-12-31
Applicant: Texas Instruments Incorporated
Inventor： Salvatore Luciano Finocchiaro , Tolga Dine , Gerd Schuppener , Siraj Akhtar , Swaminathan Sankaran , Baher Haroun
Abstract: In described examples, a method of operating a charge pump includes a first control signal deactivating a first transistor, and the first control signal's logical complement activating a second transistor to reset the first transistor's DC bias voltage. The first control signal's logical complement deactivates the second transistor, and the first control signal provides a bias voltage to the first transistor to activate it, causing current to be transmitted from an input voltage to an output terminal. A second control signal deactivates a third transistor, and the second control signal's logical complement activates a fourth transistor to reset the second transistor's DC bias voltage. The second control signal's logical complement deactivates the fourth transistor, and the second control signal provides a bias voltage to the third transistor to activate it, causing current to be transmitted from the output terminal to a ground.
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公开(公告)号：US20210203329A1
公开(公告)日：2021-07-01
申请号：US16731739
申请日：2019-12-31
Applicant: Texas Instruments Incorporated
Inventor： Salvatore Luciano Finocchiaro , Tolga Dinc , Gerd Schuppener , Siraj Akhtar , Swaminathan Sankaran , Baher Haroun
Abstract: In described examples, a method of operating a charge pump includes a first control signal deactivating a first transistor, and the first control signal's logical complement activating a second transistor to reset the first transistor's DC bias voltage. The first control signal's logical complement deactivates the second transistor, and the first control signal provides a bias voltage to the first transistor to activate it, causing current to be transmitted from an input voltage to an output terminal. A second control signal deactivates a third transistor, and the second control signal's logical complement activates a fourth transistor to reset the second transistor's DC bias voltage. The second control signal's logical complement deactivates the fourth transistor, and the second control signal provides a bias voltage to the third transistor to activate it, causing current to be transmitted from the output terminal to a ground.
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公开(公告)号：US10181834B2
公开(公告)日：2019-01-15
申请号：US15672070
申请日：2017-08-08
Applicant: Texas Instruments Incorporated
Inventor： Siraj Akhtar , Richard Francis Taylor , Petteri Litmanen
IPC: H01L23/522 , H03H7/42 , H01L23/64 , H01L23/66 , H01L49/02 , H01F21/12 , H01F27/28 , H01F27/29 , H01F41/04
Abstract: In described examples of a magnetically coupled structure on a substrate with an integrated circuit device, the structure includes a first coil in a differential configuration, a second coil located above the first coil in a generally stacked configuration, and a center tap connection to a winding of the second coil. The first coil includes a first differential terminal, a second differential terminal, and metal windings of the first coil. The first coil's metal windings form a continuous spiral electrical path between the first and second differential terminals. The first coil's metal windings include turns and crossing connections between the turns. The turns are fabricated in an integrated circuit metal wiring level, and the crossing connections are fabricated in at least one metal level other than the metal wiring level containing the turns. The center tap is positioned to create a balanced structure.
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公开(公告)号：US20160142036A1
公开(公告)日：2016-05-19
申请号：US15003030
申请日：2016-01-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Siraj Akhtar , Richard Francis Taylor , Petteri Litmanen
CPC classification number: H03H7/42 , H01F21/12 , H01F27/2804 , H01F27/29 , H01F41/041 , H01L23/5227 , H01L23/645 , H01L23/66 , H01L28/10 , H01L2223/6655 , H01L2924/0002 , H01L2924/00
Abstract: A magnetically-coupled structure is integrated with an integrated circuit in back end-of-line (BEOL) digital CMOS fabrication processes. A differential primary (or secondary) coil is formed by patterning a thick copper (Cu) metal layer, and a single-ended secondary (or primary) coil is formed by patterning a thick aluminum (Al) top metal bonding layer. Crossovers and/or cross-unders are formed using thin metal layers. One embodiment provides a stacked balun with a differential primary input winding defined in the copper layer, directly underneath a single-ended spiral winding defined in the aluminum layer. The spiral forms the single-ended secondary output of the balun and is rotated by 90° to prevent metal shorting for its cross-under connections. Another embodiment provides a transformer with one differential primary (or secondary) coil defined in the copper layer and another differential secondary (or primary) coil defined in the aluminum layer and adding a center tap. The position of the tap is selected to compensate for phase differences and provide desired balance.
Abstract translation: 磁耦合结构与后端（BEOL）数字CMOS制造工艺中的集成电路集成。 通过图案化厚铜（Cu）金属层来形成差分初级（或次级）线圈，并且通过图案化厚铝（Al）顶部金属结合层来形成单端次级（或初级）线圈。 使用薄金属层形成交叉和/或交叉下方。 一个实施例提供了一种堆叠的平衡 - 不平衡转换器，其具有限定在铜层中的差分初级输入绕组，直接位于限定在铝层中的单端螺旋绕组下方。 螺旋形成平衡 - 不平衡变换器的单端二次输出，并旋转90°，以防止金属短路其交叉连接。 另一个实施例提供一种变压器，其具有限定在铜层中的一个差分初级（或次级）线圈和限定在铝层中的另一个差分次级（或初级）线圈，并且添加中心抽头。 选择抽头的位置来补偿相位差并提供所需的平衡。
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Patent Agency Ranking
公开(公告)号：US20240355700A1
公开(公告)日：2024-10-24
申请号：US18458367
申请日：2023-08-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Siraj Akhtar , Enis Tuncer , Hiep Xuan Nguyen
IPC: H01L23/367 , H01L21/306 , H01L21/3065 , H01L21/308 , H01L23/00
CPC classification number: H01L23/367 , H01L21/30608 , H01L21/3065 , H01L21/308 , H01L24/16 , H01L24/32 , H01L24/73 , H01L2224/16059 , H01L2224/16245 , H01L2224/32245 , H01L2224/73203 , H01L2224/73253 , H01L2924/182
Abstract: The present disclosure generally relates to die-package interconnect in a semiconductor device assembly to facilitate thermal conduction. In an example, a semiconductor device assembly includes a semiconductor substrate, a metallization structure, a package substrate, a die-package interconnect, and one or more insulation layers. The metallization structure is on the semiconductor substrate and includes a first metal layer. The die-package interconnect is between the metallization structure and a second metal layer of the package substrate. The die-package interconnect overlaps at least part of a transistor on the semiconductor substrate. The insulation layer(s) are on the metallization structure and have a first portion having a first thickness and a second portion having a second thickness. The first portion is outside a footprint of the transistor. The second portion is between the die-package interconnect and the at least part of the transistor. The first thickness being larger than the second thickness.
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公开(公告)号：US11646700B2
公开(公告)日：2023-05-09
申请号：US17353214
申请日：2021-06-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Siraj Akhtar , Swaminathan Sankaran
CPC classification number: H03F1/3223 , H03F1/3205 , H03F2200/387
Abstract: A circuit includes a main amplifier having a first input and a first output. A main bias circuit is coupled to the main amplifier, and the main bias circuit configured to operate the main amplifier in a first frequency band. A feedforward cancellation amplifier has a second input and a second output, in which the second input is coupled to the first input, and the second output is coupled to the first output. A filter is coupled between the first input and the second input. A feedforward bias circuit is coupled to the feedforward cancellation amplifier. The feedforward bias circuit is configured to operate the feedforward cancellation amplifier in a second frequency band within and narrower than the first frequency band.
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公开(公告)号：US11411566B2
公开(公告)日：2022-08-09
申请号：US17397954
申请日：2021-08-09
Applicant: Texas Instruments Incorporated
Inventor： Salvatore Luciano Finocchiaro , Tolga Dine , Gerd Schuppener , Siraj Akhtar , Swaminathan Sankaran , Baher Haroun
Abstract: In described examples, a method of operating a charge pump includes a first control signal deactivating a first transistor, and the first control signal's logical complement activating a second transistor to reset the first transistor's DC bias voltage. The first control signal's logical complement deactivates the second transistor, and the first control signal provides a bias voltage to the first transistor to activate it, causing current to be transmitted from an input voltage to an output terminal. A second control signal deactivates a third transistor, and the second control signal's logical complement activates a fourth transistor to reset the second transistor's DC bias voltage. The second control signal's logical complement deactivates the fourth transistor, and the second control signal provides a bias voltage to the third transistor to activate it, causing current to be transmitted from the output terminal to a ground.
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公开(公告)号：US09699705B2
公开(公告)日：2017-07-04
申请号：US13901814
申请日：2013-05-24
Applicant: Texas Instruments Incorporated
Inventor： Nirmal Chindhu Warke , Srinath Hosur , Martin J. Izzard , Siraj Akhtar , Baher S. Haroun , Marco Corsi
IPC: H04W40/00 , H01Q3/26 , H01Q21/00 , H04L12/935 , H04L12/931 , H04W40/06 , H04W40/12
CPC classification number: H04W40/00 , H01Q3/26 , H01Q9/20 , H01Q21/0006 , H01Q21/0037 , H04B7/0617 , H04B17/336 , H04L45/74 , H04L49/3009 , H04L49/40 , H04W40/06 , H04W40/12 , Y02D70/00 , Y02D70/166 , Y02D70/322 , Y02D70/34
Abstract: Embodiments of the invention provide a system and method for chip to chip communications in electronic circuits. A router or switch receives data packets at input port ASICs. A routing table on the input port ASIC or on a routing ASIC is used to identify a destination port ASIC based upon header information in the data packet. The data packet is transmitted from the input port ASIC to the destination port ASIC using millimeter wave signals that are transmitted across a waveguide or a wireless interface.
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公开(公告)号：US20130258892A1
公开(公告)日：2013-10-03
申请号：US13901814
申请日：2013-05-24
Applicant: Texas Instruments Incorporated
Inventor： Nirmal Chindhu Warke , Srinath Hosur , Martin J. Izzard , Siraj Akhtar , Baher S. Haroun , Marco Corsi
IPC: H04W40/00
CPC classification number: H04W40/00 , H01Q3/26 , H01Q9/20 , H01Q21/0006 , H01Q21/0037 , H04B7/0617 , H04B17/336 , H04L45/74 , H04L49/3009 , H04L49/40 , H04W40/06 , H04W40/12 , Y02D70/00 , Y02D70/166 , Y02D70/322 , Y02D70/34
Abstract: Embodiments of the invention provide a system and method for chip to chip communications in electronic circuits. A router or switch receives data packets at input port ASICs. A routing table on the input port ASIC or on a routing ASIC is used to identify a destination port ASIC based upon header information in the data packet. The data packet is transmitted from the input port ASIC to the destination port ASIC using millimeter wave signals that are transmitted across a waveguide or a wireless interface.
Abstract translation: 本发明的实施例提供了一种用于电子电路中芯片到芯片通信的系统和方法。 路由器或交换机在输入端口ASIC处接收数据包。 输入端口ASIC或路由ASIC上的路由表用于根据数据包中的报头信息识别目标端口ASIC。 使用在波导或无线接口上传输的毫米波信号，将数据分组从输入端口ASIC发送到目标端口ASIC。
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