公开(公告)号：US20250165688A1

公开(公告)日：2025-05-22

申请号：US18513070

申请日：2023-11-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lakshmanan Balasubramanian ,  Rubin Parekhji ,  Supraja Ramakrishnan

IPC: G06F30/3308 ,  G06F119/02

Abstract: A method comprises creating an electronic circuit design having a plurality of electronic components, defining a fault condition imposable during a simulation of the electronic circuit design, and generating a simulation model based on the electronic circuit design. The method also comprises generating a simulation fault model representing the fault condition and executing a simulation of the simulation model to simulate operation of the electronic circuit design. During the execution of the simulation, the method comprises controlling the simulation fault model to begin an imposition of the fault condition within the simulation model, simulating circuit behavior of the simulation model in response to the imposition of the fault condition, controlling the simulation fault model to cease the imposition of the fault condition within the simulation model, and simulating circuit behavior of the simulation model in response to the cessation of the imposition of the fault condition.

公开(公告)号：US20230367938A1

公开(公告)日：2023-11-16

申请号：US18315076

申请日：2023-05-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vivek Gandhi ,  Ramakrishnan Venkatraman ,  Lakshmanan Balasubramanian ,  Harsh Kumar Sharma

IPC: G06F30/333 ,  G06F30/3308

CPC classification number: G06F30/333 ,  G06F30/3308

Abstract: A method comprises creating an electronic module design having a plurality of electronic components comprising a plurality of low power enabled components and defining a model of functional behavior and of power behavior. The method also comprises identifying sequential element information correlated with an electronic component based on the models of functional and power behavior. the sequential element information comprising a first control signal and a second control signal. A coverage test is generated based on the sequential element information and is configured to quantify behavior of the electronic component based on a relationship of a plurality of activation states of a first control signal to a plurality of activation states of a second control signal. A simulation file is run to simulate operation of the electronic module design, and a performance status of the electronic module design is determined in response to running the simulation file.

公开(公告)号：US20210208197A1

公开(公告)日：2021-07-08

申请号：US17139246

申请日：2020-12-31

Applicant: Texas Instruments Incorporated

Inventor： Guha Lakshmanan ,  Rakesh Hariharan ,  Lakshmanan Balasubramanian

IPC: G01R31/317 ,  G01R3/00

Abstract: A packaged electronic device has a die with a load circuit, a resistor and an analog to digital converter (ADC). The resistor is coupled between a supply node of the die and a power input of the load circuit. The ADC has a first input coupled to a first terminal of the resistor, and a second input coupled to a second terminal of the resistor to measure a voltage across the resistor while a supply voltage is applied to the supply node to determine a load current conducted by the load circuit. A method of manufacturing a packaged electronic device includes wafer processing to fabricate the load circuit, the resistor and the ADC on or in a die area of the wafer with the resistor coupled between the power input of the load circuit and the supply node of the die area.

公开(公告)号：US20200057106A1

公开(公告)日：2020-02-20

申请号：US16538518

申请日：2019-08-12

Applicant: Texas Instruments Incorporated

Inventor： Lakshmanan Balasubramanian ,  Nadeem Husain Tehsildar ,  Rubin Ajit Parekhji ,  Suresh Mallala ,  Nitin Agarwal

IPC: G01R31/3183 ,  G01R31/3167 ,  H03M1/10 ,  G06F17/50

Abstract: In one embodiment, a method of operating a computational system to evaluate a device under test, where the device under test is operable to receive a digital code input and output in response a corresponding output. The method injects a plurality of simulated faults into a pre-silicon model of the device under test. For each injected simulated fault, the method inputs a plurality of digital codes to the model. For each input digital code, the method selectively stores the input digital code if a difference, between a corresponding output for the input digital code and a no-fault output for the input, exceeds a predetermined threshold value.

公开(公告)号：US20230143500A1

公开(公告)日：2023-05-11

申请号：US17871205

申请日：2022-07-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lakshmanan Balasubramanian ,  Rubin Parekhji ,  Kalyan Chakravarthi Chekuri ,  Swathi G

IPC: G01R31/3183

CPC classification number: G01R31/31835 ,  G01R31/318307 ,  G01R31/318357

Abstract: A method for evaluating tests for fabricated integrated circuit (IC) chips includes providing, design for fault injection (DfFI) instances of an IC design that characterize activatable states of controllable elements in an IC chip based on the IC design. The method also includes fault simulating the IC design a corresponding identified test suite to determine a signature for faults and simulating the IC design with the DfFI instances activated to determine a signature for the DfFI instances. The method includes generating a DfFI-fault equivalence dictionary based on a comparison of the signature of the faults and DfFI instances and generating tests for a fabricated IC chip based on the IC design. The method includes receiving test result data characterizing the tests being applied against the fabricated IC chip with the DfFI instances activated and analyzing the test result data to determine an ability of the tests to detect the faults.

公开(公告)号：US11574099B2

公开(公告)日：2023-02-07

申请号：US17393263

申请日：2021-08-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lakshmanan Balasubramanian ,  Venkatraman Ramakrishnan

IPC: G06F30/3308 ,  G06F30/327 ,  G06F30/323 ,  G06F30/337 ,  G06F30/367 ,  G06F30/373 ,  G06F119/06 ,  G06F119/18

Abstract: A method comprises creating an electronic module design having a plurality of electronic components and defining a model of functional behavior of a subset of the plurality of electronic components, the subset of the plurality of electronic components excluding a first electronic component. Functional behavior of the first electronic component is defined in a user-defined functional design intent file based on a first template, and a power behavior of the first electronic component is defined in a user-defined power design intent file based on a second template. A simulation file is generated based on the model of functional behavior and based on the functional behavior and the power behavior of the first electronic component. The simulation file is run to simulate operation of the electronic module design. A performance status is determined of the electronic module design in response to running the simulation file.

公开(公告)号：US20220083718A1

公开(公告)日：2022-03-17

申请号：US17393263

申请日：2021-08-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lakshmanan Balasubramanian ,  Venkatraman Ramakrishnan

IPC: G06F30/3308

Abstract: A method comprises creating an electronic module design having a plurality of electronic components and defining a model of functional behavior of a subset of the plurality of electronic components, the subset of the plurality of electronic components excluding a first electronic component. Functional behavior of the first electronic component is defined in a user-defined functional design intent file based on a first template, and a power behavior of the first electronic component is defined in a user-defined power design intent file based on a second template. A simulation file is generated based on the model of functional behavior and based on the functional behavior and the power behavior of the first electronic component. The simulation file is run to simulate operation of the electronic module design. A performance status is determined of the electronic module design in response to running the simulation file.

公开(公告)号：US11994559B2

公开(公告)日：2024-05-28

申请号：US17871205

申请日：2022-07-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lakshmanan Balasubramanian ,  Rubin Parekhji ,  Kalyan Chakravarthi Chekuri ,  Swathi G

IPC: G01R31/3183 ,  G06F30/30

CPC classification number: G01R31/31835 ,  G01R31/318307 ,  G01R31/318357 ,  G06F30/30

Abstract: A method for evaluating tests for fabricated integrated circuit (IC) chips includes providing, design for fault injection (DfFI) instances of an IC design that characterize activatable states of controllable elements in an IC chip based on the IC design. The method also includes fault simulating the IC design a corresponding identified test suite to determine a signature for faults and simulating the IC design with the DfFI instances activated to determine a signature for the DfFI instances. The method includes generating a DfFI-fault equivalence dictionary based on a comparison of the signature of the faults and DfFI instances and generating tests for a fabricated IC chip based on the IC design. The method includes receiving test result data characterizing the tests being applied against the fabricated IC chip with the DfFI instances activated and analyzing the test result data to determine an ability of the tests to detect the faults.

公开(公告)号：US11815971B2

公开(公告)日：2023-11-14

申请号：US17156910

申请日：2021-01-25

Applicant: Texas Instruments Incorporated

Inventor： Lakshmanan Balasubramanian ,  Aswani Kumar Golla ,  Venkatraman Ramakrishnan ,  Sushmitha Tudiyadka Girijashankar

IPC: G06F30/30 ,  G06F1/26 ,  G06F30/38 ,  H03K3/037

CPC classification number: G06F1/266 ,  G06F30/38 ,  H03K3/037

Abstract: A method for boundary port modelling that correctly handles back-to-back isolation intent, level shifter intent and voltage level association, by providing hard association of power domains to soft data objects, such as wires. The method includes identifying a boundary port in a detailed power intent (DPI) for a soft design object (SDO). A non-wire object is inserted in the SDO for the boundary port. In the DPI, a power domain of the boundary port is assigned to the non-wire object.

公开(公告)号：US08901968B2

公开(公告)日：2014-12-02

申请号：US13930087

申请日：2013-06-28

Applicant: Texas Instruments Incorporated

Inventor： Lakshmanan Balasubramanian ,  Ranjit Kumar Dash

IPC: H03M1/00 ,  H03L5/00 ,  H02J1/00 ,  H03K19/00

CPC classification number: H02J1/00 ,  H03K19/0013 ,  Y10T307/50

Abstract: A circuit includes circuit portions operating from separate power supplies which are switched sequentially. An output of a first portion powered by a power supply (A) is provided as an input to a second portion powered by another power supply (B). Power supply (A) is switched-ON a delay interval later than power supply (B). In an embodiment, the first portion also receives a control input which enables or disables response of the first portion to changes in its inputs. An active circuit is connected between the control terminal and a constant reference potential node of the circuit, and has one transistor of a current-mirror pair connected across supplies (A) and (B). The active circuit connects the control terminal to the constant reference potential node in the delay interval, but is an open circuit otherwise. Power dissipation in the circuit is thereby reduced.

Abstract translation: 电路包括从分开的电源操作的电路部分，其被顺序地切换。 由电源（A）供电的第一部分的输出被提供给由另一电源（B）供电的第二部分的输入。 电源（A）在电源（B）之后的延迟时间间隔内接通。 在一个实施例中，第一部分还接收控制输入，其使能或禁止第一部分对其输入的变化的响应。 有源电路连接在控制端和电路的恒定参考电位节点之间，并且具有连接在电源（A）和（B）之间的电流镜对的一个晶体管。 有源电路在延迟时间间隔内将控制端子连接到恒定参考电位节点，否则就是开路。 从而减小了电路中的功耗。