公开(公告)号：US10374100B2

公开(公告)日：2019-08-06

申请号：US15637986

申请日：2017-06-29

Applicant: Texas Instruments Incorporated

Inventor： Doug Weiser ,  Jack G. Qian

IPC: H01L29/788 ,  H01L29/02 ,  H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L27/11517 ,  H01L21/8234 ,  H01L21/265

Abstract: In one disclosed embodiment, a non-volatile memory cell is constructed using a floating gate transistor with a channel that includes a buried channel region interposed between two surface channel regions under a floating gate. The surface channel regions are formed using angled lightly-doped drain implantation at locations in the substrate so that a first surface channel region is located under a first end of the floating gate and a second surface channel region is located under a second end of the floating gate. In one embodiment, the floating gate transistor is a PMOS transistor, with the channel being formed in an n-well formed in a p-type substrate, with the buried channel region being formed using a Vtp implant, and with the surface channel regions being formed using angled NLDD implants. The surface channel regions increase the energy barrier along the channel and reduce off state current of the memory cell.

公开(公告)号：US20240405125A1

公开(公告)日：2024-12-05

申请号：US18326628

申请日：2023-05-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jack G. Qian ,  Doug Weiser ,  Kemal T. San

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/66

Abstract: The present disclosure generally relates to a buried channel semiconductor device that includes one or more energy barrier modulation regions. In an example, a device includes a source/drain region, an energy barrier modulation region, a channel covering surface region, and a gate structure. The source/drain region is in a doped region in a semiconductor substrate that has an upper surface. The energy barrier modulation and channel covering surface regions are in the doped region and at the upper surface. The gate structure is over the upper surface. The energy barrier modulation and channel covering surface regions underlie the gate structure. The energy barrier modulation region is laterally between the source/drain and channel covering surface regions. The doped and energy barrier modulation regions are doped with a first conductivity type, and the source/drain and channel covering surface regions are doped with a second conductivity type opposite from the first conductivity type.