公开(公告)号：US20190198352A1

公开(公告)日：2019-06-27

申请号：US15853345

申请日：2017-12-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Amit Sureshkumar NANGIA ,  Siva Prakash GURRUM ,  Janakiraman SEETHARAMAN

IPC: H01L21/56 ,  H01L23/29 ,  H01L23/495 ,  H01L23/50 ,  H01L23/64 ,  H01L23/522 ,  H01L23/00 ,  C08G59/18

CPC classification number: H01L21/565 ,  C08G59/18 ,  H01L23/295 ,  H01L23/3135 ,  H01L23/495 ,  H01L23/49541 ,  H01L23/50 ,  H01L23/5223 ,  H01L23/562 ,  H01L23/642 ,  H01L24/03

Abstract: A semiconductor package includes an integrated circuit formed on a semiconductor substrate. A stress buffer layer is provided on the integrated circuit. Further, a mold compound is provided on a surface of the stress buffer layer opposite the integrated circuit. The mold compound comprises a resin. The resin includes filler particles. The filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns.

公开(公告)号：US20190386670A1

公开(公告)日：2019-12-19

申请号：US16555265

申请日：2019-08-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sovan GHOSH ,  Amal Kumar KUNDU ,  Janakiraman SEETHARAMAN

IPC: H03M1/08 ,  H03K5/24

Abstract: A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.

公开(公告)号：US20190181873A1

公开(公告)日：2019-06-13

申请号：US15837040

申请日：2017-12-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sovan Ghosh ,  Amal Kumar Kundu ,  Janakiraman SEETHARAMAN

IPC: H03M1/08 ,  H03K5/24

CPC classification number: H03M1/089 ,  H03K5/2481

Abstract: A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.