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公开(公告)号:US11558044B2
公开(公告)日:2023-01-17
申请号:US16950245
申请日:2020-11-17
IPC分类号: H03K5/1252 , H03K17/687 , H03K17/0416 , H03K5/00
摘要: An Inter-IC interface with a glitch filter including at least two cascaded RC filters configured to compensate a signal skew of the data or clock signal received from a data communication or clock signal line, feedback switches configured to pull up or pull down a voltage at an output node of each of the at least two cascaded RC filters, and feedforward transistors configured to condition a respective switch to the feedback switches to accelerate the pull up or the pull down.