公开(公告)号：US11063580B2

公开(公告)日：2021-07-13

申请号：US16930861

申请日：2020-07-16

Applicant: Texas Instruments Incorporated

Inventor： Pranshu Kalra ,  Srikanth Srinivasan ,  Devraj Rajagopal

IPC: H03K17/687 ,  H03K5/01 ,  H03K19/20 ,  H03K19/0175 ,  H03K19/0185 ,  H03K17/06

Abstract: A receiver includes a low-side buffer having an input terminal coupled to receive an input signal and having an output terminal coupled to a buffer terminal. Responsive to the input signal being LOW, the low-side buffer is configured to couple the buffer terminal to ground. The receiver also includes a high-side buffer having an input terminal coupled to receive the input signal and having an output terminal coupled to the buffer terminal. Responsive to the input signal being HIGH, the high-side buffer is configured to provide an I/O voltage at the buffer terminal. The receiver also includes an output stage coupled to the buffer terminal and having a low voltage terminal configured to receive a low supply voltage. The output stage is configured to provide an output signal responsive to the I/O voltage at the buffer terminal, wherein the output signal is lower than the I/O voltage.

公开(公告)号：US11139807B2

公开(公告)日：2021-10-05

申请号：US16937712

申请日：2020-07-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajat Chauhan ,  Srikanth Srinivasan

IPC: H03K19/094 ,  G11C16/06 ,  G11C16/12 ,  H03K5/24 ,  H03K3/356

Abstract: A circuit that includes a first diode, a second diode, a comparator having a comparator first arm and a comparator second arm, and an inverter. The first diode has a first terminal coupled to a first node and a second terminal. The second diode is coupled in series between the second terminal of the first diode and a second node. The comparator first arm includes a first plurality of transistor devices and is coupled to a third node. The comparator second arm includes a second plurality of transistor devices and is coupled to the second node, wherein the second plurality of transistor devices is greater in number than the first plurality of transistor devices. The inverter has an input coupled to the comparator and an output coupled to a fourth node.

公开(公告)号：US10673436B1

公开(公告)日：2020-06-02

申请号：US16538513

申请日：2019-08-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bharat Gajanan Hegde ,  Devraj Matharampallil Rajagopal ,  Srikanth Srinivasan

IPC: H03K19/007 ,  H03K17/0814 ,  H03K3/3562 ,  H03K19/17788

Abstract: A device includes a failsafe circuit having a supply node configured to couple to a supply voltage source, a pad node configured to couple to an input/output (I/O) pin, and a bulk node configured to couple to a bulk of a transistor coupled to the I/O pin. The failsafe circuit is configured to assert a failsafe indicator signal when the supply node voltage falls below the pad node voltage by a threshold voltage, and couple the higher of the supply node voltage and the pad node voltage to the bulk node. The device also includes a pull-down stack coupled to the failsafe circuit and to a ground node, and a sub-circuit configured to turn off the pull-down stack in response to the supply node discharging to the threshold voltage below the pad node voltage.

公开(公告)号：US20210119620A1

公开(公告)日：2021-04-22

申请号：US16930861

申请日：2020-07-16

Applicant: Texas Instruments Incorporated

Inventor： Pranshu Kalra ,  Srikanth Srinivasan ,  Devraj Rajagopal

IPC: H03K5/01 ,  H03K17/687 ,  H03K19/20

Abstract: A receiver includes a low-side buffer having an input terminal coupled to receive an input signal and having an output terminal coupled to a buffer terminal. Responsive to the input signal being LOW, the low-side buffer is configured to couple the buffer terminal to ground. The receiver also includes a high-side buffer having an input terminal coupled to receive the input signal and having an output terminal coupled to the buffer terminal. Responsive to the input signal being HIGH, the high-side buffer is configured to provide an I/O voltage at the buffer terminal. The receiver also includes an output stage coupled to the buffer terminal and having a low voltage terminal configured to receive a low supply voltage. The output stage is configured to provide an output signal responsive to the I/O voltage at the buffer terminal, wherein the output signal is lower than the I/O voltage.

公开(公告)号：US11558044B2

公开(公告)日：2023-01-17

申请号：US16950245

申请日：2020-11-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jhankar Malakar ,  Srikanth Srinivasan ,  Devraj Matharampallil Rajagopal

IPC: H03K5/1252 ,  H03K17/687 ,  H03K17/0416 ,  H03K5/00

Abstract: An Inter-IC interface with a glitch filter including at least two cascaded RC filters configured to compensate a signal skew of the data or clock signal received from a data communication or clock signal line, feedback switches configured to pull up or pull down a voltage at an output node of each of the at least two cascaded RC filters, and feedforward transistors configured to condition a respective switch to the feedback switches to accelerate the pull up or the pull down.

公开(公告)号：US10763839B2

公开(公告)日：2020-09-01

申请号：US16357975

申请日：2019-03-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajat Chauhan ,  Srikanth Srinivasan

IPC: H03K19/094 ,  G11C16/06 ,  G11C16/12 ,  H03K5/24 ,  H03K3/356

Abstract: Aspects of the present disclosure provide for a circuit. In at least some examples, the circuit includes a first diode, a second diode, a comparator having a comparator first arm and a comparator second arm, and an inverter. The first diode has a first terminal coupled to a first node and a second terminal. The second diode is coupled in series between the second terminal of the first diode and a second node. The comparator first arm includes a first plurality of transistor devices and is coupled to a third node. The comparator second arm includes a second plurality of transistor devices and is coupled to the second node, wherein the second plurality of transistor devices is greater in number than the first plurality of transistor devices. The inverter has an input coupled to the comparator and an output coupled to a fourth node.

公开(公告)号：US10666257B1

公开(公告)日：2020-05-26

申请号：US16502198

申请日：2019-07-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srikanth Srinivasan ,  Devraj Rajagopal

IPC: H03K19/007 ,  H03K19/0185

Abstract: A wide-voltage range, failsafe output interface module including a low-voltage, drain extended MOSFETs has been proposed to prevent the flow of reverse current during a failsafe operation while ensuring the MOSFETs are not subject to voltage over their voltage tolerance levels, improving reliability of an output interface module without resorting to more costly transistors with thicker films.