公开(公告)号：US12182060B2

公开(公告)日：2024-12-31

申请号：US18190222

申请日：2023-03-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jian Wang

IPC: G06F13/42 ,  G06F15/78

Abstract: A system timer bus used by the processor elements in an ARM-based system on a chip (SoC) is driven using a Precision Time Measurement (PTM) value. This allows the processor elements to be synchronized to the PCIe ports that use PTM. When two SoCs are connected using PCIe links, this example allows the processor elements in both SoCs to be synchronized. As the processor elements are synchronized, associated tasks on the two SoCs are synchronized, so that overall operations are synchronized.

公开(公告)号：US09185421B2

公开(公告)日：2015-11-10

申请号：US13632630

申请日：2012-10-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jian Wang ,  Thanh Thien Tran ,  Gang Hua ,  Ivan Garcia

IPC: H04N19/40 ,  H04N19/59

CPC classification number: H04N19/40 ,  H04N19/59

Abstract: A video transcoding system includes a video decoder, a video encoder, and a video interface. The video decoder is configured to decode a received video signal. The video encoder is configured to encode video data decoded from the received video signal by the video decoder. The video interface couples an output of the video decoder to an input of the video encoder and is configured to transfer video data having a first chroma subsampling ratio. The video decoder is further configured to provide video data having a second chroma subsampling ratio that includes fewer chrominance samples than the first chroma sampling ratio to the video interface, and to provide non-video information generated from decoding the received video signal to the video interface using video interface bandwidth usable based on a difference between the first chroma subsampling ratio and the second chroma subsampling ratio.

Abstract translation: 视频转码系统包括视频解码器，视频编码器和视频接口。 视频解码器被配置为对接收到的视频信号进行解码。 视频编码器被配置为对由视频解码器从接收到的视频信号解码的视频数据进行编码。 视频接口将视频解码器的输出耦合到视频编码器的输入端，并被配置为传送具有第一色度子采样比的视频数据。 视频解码器还被配置为提供具有第二色度子采样比的视频数据，该第二色度子采样比包括比对视频接口的第一色度采样率更少的色度样本，并且提供从接收到的视频信号解码生成的非视频信息到视频接口 使用基于第一色度子采样比和第二色度子采样比之间的差可用的视频接口带宽。

公开(公告)号：US11615050B2

公开(公告)日：2023-03-28

申请号：US17131180

申请日：2020-12-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jian Wang

IPC: G06F13/42 ,  G06F15/78

Abstract: A system timer bus used by the processor elements in an ARM-based system on a chip (SoC) is driven using a Precision Time Measurement (PTM) value. This allows the processor elements to be synchronized to the PCIe ports that use PTM. When two SoCs are connected using PCIe links, this example allows the processor elements in both SoCs to be synchronized. As the processor elements are synchronized, associated tasks on the two SoCs are synchronized, so that overall operations are synchronized.

公开(公告)号：US09197905B2

公开(公告)日：2015-11-24

申请号：US13632636

申请日：2012-10-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jian Wang ,  Thanh Thien Tran ,  Gang Hua ,  Ivan Garcia

IPC: H04N19/40 ,  H04N19/88 ,  H04N19/46 ,  H04N19/186

CPC classification number: H04N19/88 ,  H04N19/186 ,  H04N19/40 ,  H04N19/46

Abstract: A video system includes a first video device. The first video device includes a video output port and an arbitrary data scrambler. The first video device transmits a video stream through the video output port. The video output port is configured to insert video timing reference values into the video stream. The arbitrary data scrambler is configured to scramble non-video data for transmission in the video stream such that unscrambled non-video data containing video timing reference values is transformed, without information loss, to scrambled non-video data containing no video timing reference values.

Abstract translation: 视频系统包括第一视频设备。 第一视频设备包括视频输出端口和任意数据加扰器。 第一视频设备通过视频输出端口发送视频流。 视频输出端口被配置为将视频定时参考值插入到视频流中。 任意数据扰频器被配置为对非视频数据进行扰频，以便在视频流中进行传输，使得包含视频定时参考值的未加扰的非视频数据在没有信息丢失的情况下被变换到不包含视频定时参考值的加扰的非视频数据。

公开(公告)号：US08890599B1

公开(公告)日：2014-11-18

申请号：US14098142

申请日：2013-12-05

Applicant: Texas Instruments Incorporated

Inventor： Ming Xiao ,  Jian Wang

IPC: H03K5/08

CPC classification number: H03K5/08 ,  H02H9/041 ,  H03K3/02337 ,  H03K5/2481

Abstract: A circuit includes a comparator to generate a clamp output signal by monitoring an output voltage and a reference voltage that sets a clamp voltage threshold for the output voltage. The clamp output signal is employed to limit an input voltage from exceeding the clamp voltage threshold. A first switch supplies the reference voltage to the comparator. The first switch forms a portion of an intrinsic delay circuit with a first feedback path in the comparator to mitigate ripple in the output voltage. A second switch is coupled to the input voltage and a second feedback path in the comparator. The second switch forms another portion of the intrinsic delay circuit with the first switch, the first feedback path, and the second feedback path in the comparator to further mitigate ripple in the output voltage.

Abstract translation: 电路包括比较器，用于通过监视输出电压和为输出电压设定钳位电压阈值的参考电压来产生钳位输出信号。 采用钳位输出信号来限制输入电压超过钳位电压阈值。 第一个开关将参考电压提供给比较器。 第一开关在比较器中形成具有第一反馈路径的本征延迟电路的一部分，以减轻输出电压中的纹波。 第二开关耦合到比较器中的输入电压和第二反馈路径。 第二开关通过比较器中的第一开关，第一反馈路径和第二反馈路径形成本征延迟电路的另一部分，以进一步减轻输出电压中的纹波。