公开(公告)号：US11876530B2

公开(公告)日：2024-01-16

申请号：US17491391

申请日：2021-09-30

Applicant: Texas Instruments Incorporated

Inventor： Atul Kumar Agrawal ,  Kanak Chandra Das

IPC: H03M1/78 ,  H03M1/74 ,  H03M1/66

CPC classification number: H03M1/785 ,  H03M1/662 ,  H03M1/742

Abstract: An example apparatus includes: a voltage-to-current circuit including a first input terminal, a first output terminal and a second output terminal, a subtraction circuit including a second input terminal and a third output terminal, the second input terminal coupled to the second output terminal, a first driver circuit including a third input terminal and a fourth output terminal, the third input terminal coupled to the third output terminal, and a second driver circuit including a fourth input terminal and a fifth output terminal, the fourth input terminal coupled to the first output terminal, the fifth output coupled to the fourth output terminal.

公开(公告)号：US20230100835A1

公开(公告)日：2023-03-30

申请号：US17491391

申请日：2021-09-30

Applicant: Texas Instruments Incorporated

Inventor： Atul Kumar Agrawal ,  Kanak Chandra Das

IPC: H03M1/78 ,  H03M1/66 ,  H03M1/74

Abstract: An example apparatus includes: a voltage-to-current circuit including a first input terminal, a first output terminal and a second output terminal, a subtraction circuit including a second input terminal and a third output terminal, the second input terminal coupled to the second output terminal, a first driver circuit including a third input terminal and a fourth output terminal, the third input terminal coupled to the third output terminal, and a second driver circuit including a fourth input terminal and a fifth output terminal, the fourth input terminal coupled to the first output terminal, the fifth output coupled to the fourth output terminal.

公开(公告)号：US10972092B2

公开(公告)日：2021-04-06

申请号：US16880541

申请日：2020-05-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rishubh Khurana ,  Tanmay Neema ,  Kanak Chandra Das ,  Atul Kumar Agrawal

IPC: G06F1/24 ,  H03K17/22 ,  H03K17/30

Abstract: An integrated circuit includes a power-on reset (POR) circuit and a digital logic circuit. The POR has first and second control outputs. The POR circuit is configured to generate a first control signal on the first control output responsive to a supply voltage on the supply voltage node exceeding a first threshold voltage and is configured to generate a second control signal on the second control output responsive to the supply voltage exceeding a second threshold voltage. The digital logic circuit has a first control input coupled to the first control output of the POR circuit and has a second control input coupled to the second control output of the POR circuit. The digital logic circuit is configured to initiate a first read transaction responsive to assertion of the first control signal and to initiate a second read transaction responsive to assertion of the second control signal.