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    Power-on reset circuit
    2.
    发明授权
    Power-on reset circuit 有权

    公开(公告)号：US10972092B2

    公开(公告)日：2021-04-06

    申请号：US16880541

    申请日：2020-05-21

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Rishubh Khurana ,  Tanmay Neema ,  Kanak Chandra Das ,  Atul Kumar Agrawal

    IPC: G06F1/24 ,  H03K17/22 ,  H03K17/30

    Abstract: An integrated circuit includes a power-on reset (POR) circuit and a digital logic circuit. The POR has first and second control outputs. The POR circuit is configured to generate a first control signal on the first control output responsive to a supply voltage on the supply voltage node exceeding a first threshold voltage and is configured to generate a second control signal on the second control output responsive to the supply voltage exceeding a second threshold voltage. The digital logic circuit has a first control input coupled to the first control output of the POR circuit and has a second control input coupled to the second control output of the POR circuit. The digital logic circuit is configured to initiate a first read transaction responsive to assertion of the first control signal and to initiate a second read transaction responsive to assertion of the second control signal.

    Reduction of input dependent capacitor DAC switching current in flash-SAR analog-to-digital converters
    3.
    发明授权
    Reduction of input dependent capacitor DAC switching current in flash-SAR analog-to-digital converters 有权
    在Flash-SAR模数转换器中减少输入相关电容DAC开关电流

    公开(公告)号：US09362939B1

    公开(公告)日：2016-06-07

    申请号：US14587825

    申请日：2014-12-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Shakti Shankar Rath ,  Rishubh Khurana ,  Vineet Mishra

    IPC: H03M1/14 ,  H03M1/46 ,  H03M1/00 ,  H03M1/36

    CPC classification number: H03M1/468 ,  H03M1/0614 ,  H03M1/145 ,  H03M1/361

    Abstract: Circuits and methods for reducing input dependent capacitor DAC switching current in flash-successive approximation register (SAR) analog-to-digital converters (ADCs) are disclosed. An ADC includes an M-bit flash ADC and N-bit SAR ADC. In flash conversion phase, flash ADC outputs digital signal including most significant M-bits of N-bits of digital output code for a sampled analog signal. SAR ADC includes capacitor DAC and digital engine. The capacitor DAC includes first and second set of capacitors, where first ends of the first and second set of capacitors are coupled to common terminal. The digital engine provides the N-bits of digital output code in SAR conversion phase based on the digital signal and a voltage (Vcom) at the common terminal. During flash conversion phase, second ends of the first set of capacitors are connected to Vref and Vgnd respectively so as to generate a voltage level corresponding to the digital signal as Vcom.

    Abstract translation: 公开了用于减少闪光逐次逼近寄存器（SAR）模拟 - 数字转换器（ADC）中的输入相关电容器DAC切换电流的电路和方法。 ADC包括M位闪存ADC和N位SAR ADC。 在闪存转换阶段，闪存ADC输出数字信号，包括采样模拟信号的数字输出代码的N位最高有效M位。 SAR ADC包括电容DAC和数字引擎。 电容器DAC包括第一和第二组电容器，其中第一和第二组电容器的第一端耦合到公共端子。 数字引擎基于数字信号和公共端的电压（Vcom），在SAR转换阶段提供数字输出代码的N位。 在闪光转换阶段期间，第一组电容器的第二端分别连接到Vref和Vgnd，以便产生与数字信号对应的电压电平为Vcom。

    DIGITAL-TO-ANALOG CONVERTER WITH DIGITALLY CONTROLLED TRIM
    5.
    发明公开
    DIGITAL-TO-ANALOG CONVERTER WITH DIGITALLY CONTROLLED TRIM 审中-公开

    公开(公告)号：US20230238973A1

    公开(公告)日：2023-07-27

    申请号：US17586179

    申请日：2022-01-27

    Applicant: Texas Instruments Incorporated

    Inventor： Tanmay Neema ,  Gautam Salil Nandi ,  Rishubh Khurana ,  Atul Kumar Agrawal ,  Deepak Kumar Meher

    IPC: H03M1/06

    CPC classification number: H03M1/0604

    Abstract: In described examples, a digital-to-analog converter (DAC) includes an output, a ground, a reference voltage terminal, an input code terminal, multiple switches, multiple resistors, and a controller. The switches couple to the reference voltage terminal when activated and to the ground when deactivated. The resistors are variously coupled between corresponding ones of the switches and the output, so that activating the switches causes the DAC to output an output voltage. The controller is coupled to the input code terminal and coupled to control the switches. The controller generates an output code based on an input code in response to at least one differential nonlinearity error greater than one least significant bit voltage. The input code corresponds to a first ideal output voltage, the output code corresponds to a second, different ideal output voltage. The controller generates an output voltage by controlling the switches using the output code.

    DIGITAL-TO-ANALOG CONVERTER WITH DIGITALLY CONTROLLED TRIM
    6.
    发明公开
    DIGITAL-TO-ANALOG CONVERTER WITH DIGITALLY CONTROLLED TRIM 审中-公开

    公开(公告)号：US20230238972A1

    公开(公告)日：2023-07-27

    申请号：US17586155

    申请日：2022-01-27

    Applicant: Texas Instruments Incorporated

    Inventor： Tanmay Neema ,  Gautam Salil Nandi ,  Rishubh Khurana ,  Atul Kumar Agrawal ,  Deepak Kumar Meher

    IPC: H03M1/06

    CPC classification number: H03M1/0604

    Abstract: In described examples, a digital-to-analog converter includes an output, multiple most significant bit (MSB) connector resistors each having a resistance R−ΔR, multiple least significant bit (LSB) connector resistors each having a resistance R, and multiple binary arm resistors each having a resistance 2R. The MSB connector resistors are coupled in a series beginning with the output and ending with a first one of the LSB connector resistors, and the LSB connector resistors are coupled in a series beginning with the first LSB connector resistor. A terminal of one of the binary arm resistors is coupled to an ending of the LSB connector resistor series, and a terminal of each of different remaining ones of the binary arm resistors is coupled between a different pair of the MSB and/or LSB connector resistors.

    REDUCTION OF INPUT DEPENDENT CAPACITOR DAC SWITCHING CURRENT IN FLASH-SAR ANALOG-TO-DIGITAL CONVERTERS
    7.
    发明申请
    REDUCTION OF INPUT DEPENDENT CAPACITOR DAC SWITCHING CURRENT IN FLASH-SAR ANALOG-TO-DIGITAL CONVERTERS 有权
    减少输入相关电容DAC切换电流在FLASH-SAR模拟数字转换器

    公开(公告)号：US20160191072A1

    公开(公告)日：2016-06-30

    申请号：US14587825

    申请日：2014-12-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Shakti Shankar Rath ,  Rishubh Khurana ,  Vineet Mishra

    IPC: H03M1/46 ,  H03M1/36 ,  H03M1/00

    CPC classification number: H03M1/468 ,  H03M1/0614 ,  H03M1/145 ,  H03M1/361

    Abstract: Circuits and methods for reducing input dependent capacitor DAC switching current in flash-successive approximation register (SAR) analog-to-digital converters (ADCs) are disclosed. An ADC includes an M-bit flash ADC and N-bit SAR ADC. In flash conversion phase, flash ADC outputs digital signal including most significant M-bits of N-bits of digital output code for a sampled analog signal. SAR ADC includes capacitor DAC and digital engine. The capacitor DAC includes first and second set of capacitors, where first ends of the first and second set of capacitors are coupled to common terminal. The digital engine provides the N-bits of digital output code in SAR conversion phase based on the digital signal and a voltage (Vcom) at the common terminal. During flash conversion phase, second ends of the first set of capacitors are connected to Vref and Vgnd respectively so as to generate a voltage level corresponding to the digital signal as Vcom.

    Abstract translation: 公开了用于减少闪光逐次逼近寄存器（SAR）模拟 - 数字转换器（ADC）中的输入相关电容器DAC切换电流的电路和方法。 ADC包括M位闪存ADC和N位SAR ADC。 在闪存转换阶段，闪存ADC输出数字信号，包括采样模拟信号的数字输出代码的N位最高有效M位。 SAR ADC包括电容DAC和数字引擎。 电容器DAC包括第一和第二组电容器，其中第一和第二组电容器的第一端耦合到公共端子。 数字引擎基于数字信号和公共端的电压（Vcom），在SAR转换阶段提供数字输出代码的N位。 在闪光转换阶段期间，第一组电容器的第二端分别连接到Vref和Vgnd，以便产生与数字信号对应的电压电平为Vcom。

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