公开(公告)号：US12218655B2

公开(公告)日：2025-02-04

申请号：US18126080

申请日：2023-03-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ahmed Essam Hashim ,  Karthikeyan Kandaswamy ,  Abhishek Badarinath

IPC: H03K3/00 ,  H03K5/08 ,  H03K17/10 ,  H03K17/687

Abstract: A gate driver circuit includes first through third transistors, a first voltage clamp, and control logic. The first transistor has a first control input and first and second current terminals. The first current terminal couples to a first voltage terminal. The first voltage clamp couples between the first voltage terminal and the first control input. The second transistor couples between the first control input and the second voltage terminal. The third transistor couples between the first control input and the second voltage terminal. The third transistor is smaller than the second transistor. The control logic is configured to turn on both the second and third transistors to thereby turn on the first transistor, and the first control logic configured to turn off the second transistor after the first transistor turns on while maintaining in an on-state the third transistor to maintain the first transistor in the on-state.

公开(公告)号：US20230246640A1

公开(公告)日：2023-08-03

申请号：US18126080

申请日：2023-03-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ahmed Essam Hashim ,  Karthikeyan Kandaswamy ,  Abhishek Badarinath

IPC: H03K17/10

CPC classification number: H03K17/102

Abstract: A gate driver circuit includes first through third transistors, a first voltage clamp, and control logic. The first transistor has a first control input and first and second current terminals. The first current terminal couples to a first voltage terminal. The first voltage clamp couples between the first voltage terminal and the first control input. The second transistor couples between the first control input and the second voltage terminal. The third transistor couples between the first control input and the second voltage terminal. The third transistor is smaller than the second transistor. The control logic is configured to turn on both the second and third transistors to thereby turn on the first transistor, and the first control logic configured to turn off the second transistor after the first transistor turns on while maintaining in an on-state the third transistor to maintain the first transistor in the on-state.

公开(公告)号：US11641198B1

公开(公告)日：2023-05-02

申请号：US17538953

申请日：2021-11-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ahmed Essam Hashim ,  Karthikeyan Kandaswamy ,  Abhishek Badarinath

IPC: H03K3/00 ,  H03K5/08 ,  H03K17/687 ,  H03K17/10

Abstract: A gate driver circuit includes first through third transistors, a first voltage clamp, and control logic. The first transistor has a first control input and first and second current terminals. The first current terminal couples to a first voltage terminal. The first voltage clamp couples between the first voltage terminal and the first control input. The second transistor couples between the first control input and the second voltage terminal. The third transistor couples between the first control input and the second voltage terminal. The third transistor is smaller than the second transistor. The control logic is configured to turn on both the second and third transistors to thereby turn on the first transistor, and the first control logic configured to turn off the second transistor after the first transistor turns on while maintaining in an on-state the third transistor to maintain the first transistor in the on-state.