公开(公告)号：US10361095B2

公开(公告)日：2019-07-23

申请号：US15981725

申请日：2018-05-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abbas Ali ,  Dhishan Kande ,  Qi-Zhong Hong ,  Young-Joon Park ,  Kyle McPherson

IPC: H01L21/768 ,  H01L21/3213

Abstract: A method of fabricating an integrated circuit (IC) includes depositing an aluminum-containing metal interconnect layer at a first temperature over a semiconductor device having a plurality of transistors. The metal interconnect layer is annealed at a maximum annealing temperature that is less than the first temperature. The metal interconnect layer is patterned after the annealing, thereby interconnecting the transistors.

公开(公告)号：US10002774B1

公开(公告)日：2018-06-19

申请号：US15697098

申请日：2017-09-06

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali ,  Dhishan Kande ,  Qi-Zhong Hong ,  Young-Joon Park ,  Kyle McPherson

IPC: H01L21/44 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L21/32136 ,  H01L21/76819 ,  H01L21/76837 ,  H01L21/76841 ,  H01L21/76885 ,  H01L23/53223

Abstract: A method of fabricating an integrated circuit (IC) includes forming a metal interconnect stack on substrate that includes a plurality of product die each having a plurality of transistors connected together to implement a circuit function. The forming the metal interconnect stack includes depositing a metal interconnect layer comprising aluminum on a barrier layer at a first temperature. After depositing the metal interconnect layer, the metal interconnect stack is annealed in a non-oxidizing ambient at a maximum annealing temperature that is