公开(公告)号：US11848268B2

公开(公告)日：2023-12-19

申请号：US17378203

申请日：2021-07-16

Applicant: Texas Instruments Incorporated

Inventor： Dhishan Kande ,  Qi-Zhong Hong ,  Abbas Ali ,  Gregory B. Shinn

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H01L23/532

CPC classification number: H01L23/5228 ,  H01L21/76805 ,  H01L23/5226 ,  H01L28/24 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266

Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.

公开(公告)号：US11101212B2

公开(公告)日：2021-08-24

申请号：US16423723

申请日：2019-05-28

Applicant: Texas Instruments Incorporated

Inventor： Dhishan Kande ,  Qi-Zhong Hong ,  Abbas Ali ,  Gregory B. Shinn

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H01L23/532

Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.

公开(公告)号：US10361095B2

公开(公告)日：2019-07-23

申请号：US15981725

申请日：2018-05-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abbas Ali ,  Dhishan Kande ,  Qi-Zhong Hong ,  Young-Joon Park ,  Kyle McPherson

IPC: H01L21/768 ,  H01L21/3213

Abstract: A method of fabricating an integrated circuit (IC) includes depositing an aluminum-containing metal interconnect layer at a first temperature over a semiconductor device having a plurality of transistors. The metal interconnect layer is annealed at a maximum annealing temperature that is less than the first temperature. The metal interconnect layer is patterned after the annealing, thereby interconnecting the transistors.

公开(公告)号：US20190221516A1

公开(公告)日：2019-07-18

申请号：US15872429

申请日：2018-01-16

Applicant: Texas Instruments Incorporated

Inventor： Dhishan Kande ,  Qi-Zhong Hong ,  Abbas Ali ,  Gregory B. Shinn

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768

CPC classification number: H01L23/5228 ,  H01L21/76805 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L28/24

Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.

公开(公告)号：US10211278B2

公开(公告)日：2019-02-19

申请号：US15646917

申请日：2017-07-11

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali ,  Dhishan Kande ,  Qi-Zhong Hong

IPC: H01L49/02 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/768 ,  H01L21/027 ,  H01L21/02 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

Abstract: A device and method for fabricating an integrated circuit (IC) chip is disclosed. The method includes depositing a first thin film resistor material on a first inter-level dielectric (ILD) layer; depositing an etch retardant layer overlying the first thin film resistor material; and patterning and etching the etch retardant layer and the first thin film resistor material to form a first resistor. The method continues with depositing a second ILD layer overlying the first resistor; and patterning and etching the second ILD layer using a first etch chemistry to form vias through the second ILD layer and the etch retardant layer to the first resistor. The etch retardant layer is selective to a first etch chemistry and the thickness of the etch retardant layer is such that the via etching process removes substantially all exposed portions of the etch retardant layer and substantially prevents consumption of the underlying first thin film resistor material.

公开(公告)号：US20190108943A1

公开(公告)日：2019-04-11

申请号：US15730508

申请日：2017-10-11

Applicant: Texas Instruments Incorporated

Inventor： Gang Liu ,  Qi-Zhong Hong

IPC: H01G4/01 ,  H01G4/04 ,  H01G4/005 ,  H01G4/18 ,  H01G4/224 ,  H01L29/66

Abstract: High voltage capacitors and methods of manufacturing the same are disclosed. An apparatus includes a first electrode of a capacitor above a semiconductor substrate. The first electrode is parallel to a plane perpendicular to the substrate. The apparatus further includes a second electrode spaced apart from the first electrode and parallel to the plane. The first electrode and the second electrode each including: (1) a first metal segment in a first metal layer, (2) a second metal segment in a second metal layer, and (3) a conductive via in an intermetal dielectric layer between the first and second metal layers interconnecting the first and second metal segments.

公开(公告)号：US10002774B1

公开(公告)日：2018-06-19

申请号：US15697098

申请日：2017-09-06

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali ,  Dhishan Kande ,  Qi-Zhong Hong ,  Young-Joon Park ,  Kyle McPherson

IPC: H01L21/44 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L21/32136 ,  H01L21/76819 ,  H01L21/76837 ,  H01L21/76841 ,  H01L21/76885 ,  H01L23/53223

Abstract: A method of fabricating an integrated circuit (IC) includes forming a metal interconnect stack on substrate that includes a plurality of product die each having a plurality of transistors connected together to implement a circuit function. The forming the metal interconnect stack includes depositing a metal interconnect layer comprising aluminum on a barrier layer at a first temperature. After depositing the metal interconnect layer, the metal interconnect stack is annealed in a non-oxidizing ambient at a maximum annealing temperature that is

公开(公告)号：US09589093B2

公开(公告)日：2017-03-07

申请号：US14577195

申请日：2014-12-19

Applicant: Texas Instruments Incorporated

Inventor： Qi-Zhong Hong

IPC: H01L21/44 ,  G06F17/50 ,  H01L23/522

CPC classification number: G06F17/5077 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/06 ,  G06F2217/12 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect. A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect using via priority groups.

Abstract translation: 一种操作计算机系统以改善具有多层互连的集成电路中的电迁移的方法。 一种操作计算机系统以通过使用经由优先级组的多电平互连的集成电路中的电迁移来改进的方法。

公开(公告)号：US10354951B1

公开(公告)日：2019-07-16

申请号：US15872429

申请日：2018-01-16

Applicant: Texas Instruments Incorporated

Inventor： Dhishan Kande ,  Qi-Zhong Hong ,  Abbas Ali ,  Gregory B. Shinn

IPC: H01L21/768 ,  H01L23/522 ,  H01L49/02 ,  H01L23/532

CPC classification number: H01L23/5228 ,  H01L21/76805 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L28/24

Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.

公开(公告)号：US20190019858A1

公开(公告)日：2019-01-17

申请号：US15646917

申请日：2017-07-11

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali ,  Dhishan Kande ,  Qi-Zhong Hong

IPC: H01L49/02 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/768 ,  H01L21/027 ,  H01L21/02 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

Abstract: A device and method for fabricating an integrated circuit (IC) chip is disclosed. The method includes depositing a first thin film resistor material on a first inter-level dielectric (ILD) layer; depositing an etch retardant layer overlying the first thin film resistor material; and patterning and etching the etch retardant layer and the first thin film resistor material to form a first resistor. The method continues with depositing a second ILD layer overlying the first resistor; and patterning and etching the second ILD layer using a first etch chemistry to form vias through the second ILD layer and the etch retardant layer to the first resistor. The etch retardant layer is selective to a first etch chemistry and the thickness of the etch retardant layer is such that the via etching process removes substantially all exposed portions of the etch retardant layer and substantially prevents consumption of the underlying first thin film resistor material.