公开(公告)号：US20230274978A1

公开(公告)日：2023-08-31

申请号：US17682617

申请日：2022-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Todd WYANT ,  Joseph LIU ,  Christopher Daniel MANACK

IPC: H01L21/78 ,  H01L21/66 ,  H01L23/544 ,  H01L23/31

CPC classification number: H01L21/78 ,  H01L22/12 ,  H01L23/544 ,  H01L23/31

Abstract: In some examples, a method for manufacturing a semiconductor package comprises coupling a photoresist layer to a non-device side of a semiconductor wafer, the semiconductor wafer having a device side, first and second circuits formed in the device side and separated by a scribe street, a test device positioned in the scribe street. The method also comprises coupling a tape to the device side of the semiconductor wafer. The method also comprises performing a photolithographic process to form an opening in the photoresist layer and plasma etching through the semiconductor wafer by way of the opening in the photoresist layer to produce first and second semiconductor dies having the first and second circuits, respectively. The method also comprises removing the tape from device sides of the first and second semiconductor dies, wherein removing the tape includes removing the test device. The method also comprises coupling the first circuit of the first semiconductor die to a conductive member. The method also comprises covering the first semiconductor die with a mold compound, the conductive member exposed to an exterior surface of the mold compound.

公开(公告)号：US20220068744A1

公开(公告)日：2022-03-03

申请号：US17003382

申请日：2020-08-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Todd WYANT ,  Matthew John SHERBIN ,  Christopher Daniel MANACK ,  Patrick Francis THOMPSON ,  You Chye HOW

IPC: H01L23/31 ,  H01L21/78 ,  H01L23/552 ,  H01L21/56 ,  H01L21/683

Abstract: In examples, a chip scale package (CSP) comprises a semiconductor die; a conductive terminal coupled to the semiconductor die; and a non-conductive coat covering a backside of the semiconductor die and a sidewall of the semiconductor die. The non-conductive coat has a thickness of less than 45 microns.