KICKBACK COMPENSATION FOR A CAPACITIVELY DRIVEN COMPARATOR

    公开(公告)号:US20200067518A1

    公开(公告)日:2020-02-27

    申请号:US16654062

    申请日:2019-10-16

    Abstract: An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference.

    KICKBACK COMPENSATION FOR A CAPACITIVELY DRIVEN COMPARATOR

    公开(公告)号:US20210013895A1

    公开(公告)日:2021-01-14

    申请号:US17039313

    申请日:2020-09-30

    Abstract: An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference.

    ANALOG-TO-DIGITAL CONVERTER
    3.
    发明申请

    公开(公告)号:US20210119638A1

    公开(公告)日:2021-04-22

    申请号:US17112095

    申请日:2020-12-04

    Abstract: An analog-to-digital converter (ADC) circuit includes a signal input terminal, a sample-and-hold circuit, and a successive approximation register (SAR) ADC. The sample-and-hold circuit includes an input terminal coupled to the signal input terminal. The SAR ADC includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to an output terminal of the sample-and-hold circuit, and an output terminal coupled to a first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal, an output terminal coupled to a second input terminal of the comparator.

    KICKBACK COMPENSATION FOR A CAPACITIVELY DRIVEN COMPARATOR

    公开(公告)号:US20190207615A1

    公开(公告)日:2019-07-04

    申请号:US15902092

    申请日:2018-02-22

    Abstract: An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference.

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