公开(公告)号：US20170126219A1

公开(公告)日：2017-05-04

申请号：US14927949

申请日：2015-10-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mohammad ELBADRY ,  Robert Floyd PAYNE ,  Gerd Schuppener

IPC: H03K5/156 ,  H02M3/07

CPC classification number: H03K5/1565 ,  H02M3/07

Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.

公开(公告)号：US20170126220A1

公开(公告)日：2017-05-04

申请号：US14927929

申请日：2015-10-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mohammad ELBADRY

IPC: H03K7/08

CPC classification number: H03K7/08 ,  H03K5/1565

Abstract: A clock generator includes a duty cycle correction circuit. The duty cycle correction circuit includes a duty cycle detector. The duty cycle detector, includes a first programmable delay element and a controller. The first programmable delay element is configured to delay a clock signal. The controller is configured to vary an amount of delay applied to the clock signal by the first programmable delay element, and to apply a delayed version of the clock signal, provided by the first programmable delay element, to locate an edge of a different version of the clock signal and measure time during which the different version of the clock is high. The controller is also configured to generate a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock signal based on measured time during which the different version of the clock is high.